17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 549f91442Ssuha * Common Development and Distribution License (the "License"). 649f91442Ssuha * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22*b5d991cdSdanice * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_PCISCH_H 277c478bd9Sstevel@tonic-gate #define _SYS_PCISCH_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #ifdef __cplusplus 327c478bd9Sstevel@tonic-gate extern "C" { 337c478bd9Sstevel@tonic-gate #endif 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate /* 367c478bd9Sstevel@tonic-gate * Performance counters information. 377c478bd9Sstevel@tonic-gate */ 387c478bd9Sstevel@tonic-gate #define SCHIZO_SHIFT_PIC0 4 397c478bd9Sstevel@tonic-gate #define SCHIZO_SHIFT_PIC1 11 407c478bd9Sstevel@tonic-gate 417c478bd9Sstevel@tonic-gate /* 427c478bd9Sstevel@tonic-gate * Schizo-specific register offsets & bit field positions. 437c478bd9Sstevel@tonic-gate */ 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate /* 467c478bd9Sstevel@tonic-gate * [msb] [lsb] 477c478bd9Sstevel@tonic-gate * 0x00 <chip_type> <version#> <module-revision#> 487c478bd9Sstevel@tonic-gate */ 497c478bd9Sstevel@tonic-gate #define SCHIZO_VER_10 CHIP_ID(PCI_CHIP_SCHIZO, 0x00, 0x00) 507c478bd9Sstevel@tonic-gate #define SCHIZO_VER_20 CHIP_ID(PCI_CHIP_SCHIZO, 0x02, 0x00) 517c478bd9Sstevel@tonic-gate #define SCHIZO_VER_21 CHIP_ID(PCI_CHIP_SCHIZO, 0x03, 0x00) 527c478bd9Sstevel@tonic-gate #define SCHIZO_VER_22 CHIP_ID(PCI_CHIP_SCHIZO, 0x04, 0x00) 537c478bd9Sstevel@tonic-gate #define SCHIZO_VER_23 CHIP_ID(PCI_CHIP_SCHIZO, 0x05, 0x00) 547c478bd9Sstevel@tonic-gate #define SCHIZO_VER_24 CHIP_ID(PCI_CHIP_SCHIZO, 0x06, 0x00) 557c478bd9Sstevel@tonic-gate #define SCHIZO_VER_25 CHIP_ID(PCI_CHIP_SCHIZO, 0x07, 0x00) 567c478bd9Sstevel@tonic-gate #define XMITS_VER_10 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x01) 577c478bd9Sstevel@tonic-gate #define XMITS_VER_21 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x03) 587c478bd9Sstevel@tonic-gate #define XMITS_VER_30 CHIP_ID(PCI_CHIP_XMITS, 0x05, 0x04) 597c478bd9Sstevel@tonic-gate #define TOMATILLO_VER_10 CHIP_ID(PCI_CHIP_TOMATILLO, 0x00, 0x00) 607c478bd9Sstevel@tonic-gate #define TOMATILLO_VER_20 CHIP_ID(PCI_CHIP_TOMATILLO, 0x01, 0x00) 617c478bd9Sstevel@tonic-gate #define TOMATILLO_VER_21 CHIP_ID(PCI_CHIP_TOMATILLO, 0x02, 0x00) 627c478bd9Sstevel@tonic-gate #define TOMATILLO_VER_22 CHIP_ID(PCI_CHIP_TOMATILLO, 0x03, 0x00) 637c478bd9Sstevel@tonic-gate #define TOMATILLO_VER_23 CHIP_ID(PCI_CHIP_TOMATILLO, 0x04, 0x00) 647c478bd9Sstevel@tonic-gate #define TOMATILLO_VER_24 CHIP_ID(PCI_CHIP_TOMATILLO, 0X05, 0X00) 657c478bd9Sstevel@tonic-gate 667c478bd9Sstevel@tonic-gate /* 677c478bd9Sstevel@tonic-gate * Offsets of Control Block registers ("reg" property 2nd entry) 687c478bd9Sstevel@tonic-gate */ 697c478bd9Sstevel@tonic-gate #define SCHIZO_CB_CSR_OFFSET 0x0 /* reg 1 */ 707c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ERRCTRL_OFFSET 0x8 717c478bd9Sstevel@tonic-gate #define SCHIZO_CB_INTCTRL_OFFSET 0x10 727c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ERRLOG_OFFSET 0x18 737c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ECCCTRL_OFFSET 0x20 747c478bd9Sstevel@tonic-gate #define SCHIZO_CB_UEAFSR_OFFSET 0x30 757c478bd9Sstevel@tonic-gate #define SCHIZO_CB_UEAFAR_OFFSET 0x38 767c478bd9Sstevel@tonic-gate #define SCHIZO_CB_CEAFSR_OFFSET 0x40 777c478bd9Sstevel@tonic-gate #define SCHIZO_CB_CEAFAR_OFFSET 0x48 787c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ESTRCTRL_OFFSET 0x50 797c478bd9Sstevel@tonic-gate #define XMITS_CB_SOFT_PAUSE_OFFSET 0x58 807c478bd9Sstevel@tonic-gate #define XMITS_CB_IO_LOOPBACK_CONTROL_OFFSET 0x60 817c478bd9Sstevel@tonic-gate #define XMITS_CB_SAF_PED_CONTROL_OFFSET 0x68 827c478bd9Sstevel@tonic-gate #define XMITS_CB_SAF_PED_LOG_OFFSET 0x70 837c478bd9Sstevel@tonic-gate #define XMITS_CB_SAF_PAR_INJECT_IMM_OFFSET 0x78 847c478bd9Sstevel@tonic-gate #define XMITS_CB_SAF_PAR_INJECT_1_OFFSET 0x80 857c478bd9Sstevel@tonic-gate #define XMITS_CB_SAF_PAR_INJECT_0_OFFSET 0x88 867c478bd9Sstevel@tonic-gate #define XMITS_CB_FIRST_ERROR_LOG 0x90 877c478bd9Sstevel@tonic-gate #define XMITS_CB_FIRST_ERROR_ADDR 0x98 887c478bd9Sstevel@tonic-gate #define XMITS_CB_PCI_LEAF_STATUS 0xA0 897c478bd9Sstevel@tonic-gate 907c478bd9Sstevel@tonic-gate /* 917c478bd9Sstevel@tonic-gate * Tomatillo only bits in IOMMU control registers. 927c478bd9Sstevel@tonic-gate */ 937c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_SEG_DISP_SHIFT 4 947c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_TSB_MAX 7 957c478bd9Sstevel@tonic-gate #define TOMATIILO_IOMMU_ERR_REG_SHIFT 24 967c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_ERRSTS_SHIFT 25 977c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_ERR (1ull << 24) 987c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_ERRSTS (3ull << 25) 997c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_ERR_ILLTSBTBW (1ull << 27) 1007c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_ERR_BAD_VA (1ull << 28) 1017c478bd9Sstevel@tonic-gate 1027c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_PROTECTION_ERR 0x0 1037c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_INVALID_ERR 0x1 1047c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_TIMEOUT_ERR 0x2 1057c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_ECC_ERR 0x3 1067c478bd9Sstevel@tonic-gate 1077c478bd9Sstevel@tonic-gate /* 1087c478bd9Sstevel@tonic-gate * Offsets of performance monitoring registers. 1097c478bd9Sstevel@tonic-gate */ 1107c478bd9Sstevel@tonic-gate #define SCHIZO_PERF_PCI_PCR_OFFSET 0x00000100 1117c478bd9Sstevel@tonic-gate #define SCHIZO_PERF_PCI_PIC_OFFSET 0x00000108 1127c478bd9Sstevel@tonic-gate #define SCHIZO_PERF_PCI_ICD_OFFSET 0x00000110 1137c478bd9Sstevel@tonic-gate #define SCHIZO_PERF_SAF_PCR_OFFSET 0x00007000 1147c478bd9Sstevel@tonic-gate #define SCHIZO_PERF_SAF_PIC_OFFSET 0x00007008 1157c478bd9Sstevel@tonic-gate 1167c478bd9Sstevel@tonic-gate /* 1177c478bd9Sstevel@tonic-gate * Offsets of registers in the PBM block: 1187c478bd9Sstevel@tonic-gate */ 1197c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_REG_OFFSET 0x2000 1207c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET 0x2010 1217c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET 0x2018 1227c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_DIAG_REG_OFFSET 0x2020 1237c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_ESTAR_REG_OFFSET 0x2028 1247c478bd9Sstevel@tonic-gate #define TOMATILLO_TGT_ADDR_SPACE_OFFSET 0x2490 1257c478bd9Sstevel@tonic-gate #define TOMATILLO_TGT_ERR_VALOG_OFFSET 0x2498 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate #define XMITS10_PCI_X_ERROR_STATUS_REG_OFFSET 0x2030 1287c478bd9Sstevel@tonic-gate #define XMITS10_PCI_X_DIAG_REG_OFFSET 0x2038 1297c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_ERROR_STATUS_REG_OFFSET 0x2300 1307c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_REG_OFFSET 0x2308 1317c478bd9Sstevel@tonic-gate #define XMITS_PARITY_DETECT_REG_OFFSET 0x2040 1327c478bd9Sstevel@tonic-gate #define XMITS_PARITY_LOG_REG_OFFSET 0x2048 1337c478bd9Sstevel@tonic-gate #define XMITS_PARITY_INJECT_REG_OFFSET 0x2050 1347c478bd9Sstevel@tonic-gate #define XMITS_PARITY_INJECT_1_REG_OFFSET 0x2058 1357c478bd9Sstevel@tonic-gate #define XMITS_PARITY_INJECT_0_REG_OFFSET 0x2060 136810a4a70Sdanice #define XMITS_UPPER_RETRY_COUNTER_REG_OFFSET 0x2310 1377c478bd9Sstevel@tonic-gate 1387c478bd9Sstevel@tonic-gate /* 1397c478bd9Sstevel@tonic-gate * Offsets of IO Cache Registers: 1407c478bd9Sstevel@tonic-gate */ 1417c478bd9Sstevel@tonic-gate #define TOMATILLO_IOC_CSR_OFF 0x2248 1427c478bd9Sstevel@tonic-gate #define TOMATILLO_IOC_TAG_OFF 0x2250 1437c478bd9Sstevel@tonic-gate #define TOMATIILO_IOC_DAT_OFF 0x2290 1447c478bd9Sstevel@tonic-gate 1457c478bd9Sstevel@tonic-gate /* 1467c478bd9Sstevel@tonic-gate * Offsets of registers in the iommu block: 1477c478bd9Sstevel@tonic-gate */ 1487c478bd9Sstevel@tonic-gate #define SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET 0x00000218 1497c478bd9Sstevel@tonic-gate #define TOMATILLO_IOMMU_ERR_TFAR_OFFSET 0x0220 1507c478bd9Sstevel@tonic-gate 1517c478bd9Sstevel@tonic-gate /* 1527c478bd9Sstevel@tonic-gate * Offsets of registers in the streaming cache block: 1537c478bd9Sstevel@tonic-gate */ 1547c478bd9Sstevel@tonic-gate #define SCHIZO_SC_CTRL_REG_OFFSET 0x00002800 1557c478bd9Sstevel@tonic-gate #define SCHIZO_SC_INVL_REG_OFFSET 0x00002808 1567c478bd9Sstevel@tonic-gate #define SCHIZO_SC_SYNC_REG_OFFSET 0x00002810 1577c478bd9Sstevel@tonic-gate #define SCHIZO_SC_CTX_INVL_REG_OFFSET 0x00002818 1587c478bd9Sstevel@tonic-gate #define SCHIZO_SC_CTX_MATCH_REG_OFFSET 0x00010000 1597c478bd9Sstevel@tonic-gate #define SCHIZO_SC_DATA_DIAG_OFFSET 0x0000b000 1607c478bd9Sstevel@tonic-gate #define SCHIZO_SC_TAG_DIAG_OFFSET 0x0000ba00 1617c478bd9Sstevel@tonic-gate #define SCHIZO_SC_LTAG_DIAG_OFFSET 0x0000bb00 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate /* 1647c478bd9Sstevel@tonic-gate * MAX_PRF when enabled will always prefetch the max of 8 1657c478bd9Sstevel@tonic-gate * prefetches if possible. 1667c478bd9Sstevel@tonic-gate */ 1677c478bd9Sstevel@tonic-gate #define XMITS_SC_MAX_PRF (0x1ull << 7) 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate /* 1707c478bd9Sstevel@tonic-gate * Offsets of registers in the PCI Idle Check Diagnostics Register. 1717c478bd9Sstevel@tonic-gate */ 1727c478bd9Sstevel@tonic-gate #define SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE 0x4000 1737c478bd9Sstevel@tonic-gate #define SCHIZO_PERF_PCI_ICD_PCI_2_0_COMPATIBLE 0x8000 1747c478bd9Sstevel@tonic-gate 1757c478bd9Sstevel@tonic-gate /* 1767c478bd9Sstevel@tonic-gate * Offsets of registers in the interrupt block: 1777c478bd9Sstevel@tonic-gate */ 1787c478bd9Sstevel@tonic-gate #define SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET 0x1100 1797c478bd9Sstevel@tonic-gate #define SCHIZO_IB_INTR_MAP_REG_OFFSET 0x1000 1807c478bd9Sstevel@tonic-gate #define SCHIZO_IB_CLEAR_INTR_REG_OFFSET 0x1400 1817c478bd9Sstevel@tonic-gate #define SCHIZO_PBM_DMA_SYNC_REG_OFFSET 0x1A08 1827c478bd9Sstevel@tonic-gate #define PBM_DMA_SYNC_COMP_REG_OFFSET 0x1A10 1837c478bd9Sstevel@tonic-gate #define PBM_DMA_SYNC_PEND_REG_OFFSET 0x1A18 1847c478bd9Sstevel@tonic-gate 1857c478bd9Sstevel@tonic-gate /* 1867c478bd9Sstevel@tonic-gate * Address space offsets and sizes: 1877c478bd9Sstevel@tonic-gate */ 1887c478bd9Sstevel@tonic-gate #define SCHIZO_SIZE 0x0000800000000000ull 1897c478bd9Sstevel@tonic-gate 1907c478bd9Sstevel@tonic-gate /* 1917c478bd9Sstevel@tonic-gate * Schizo-specific fields of interrupt mapping register: 1927c478bd9Sstevel@tonic-gate */ 1937c478bd9Sstevel@tonic-gate #define SCHIZO_INTR_MAP_REG_NID 0x0000000003E00000ull 1947c478bd9Sstevel@tonic-gate #define SCHIZO_INTR_MAP_REG_NID_SHIFT 21 1957c478bd9Sstevel@tonic-gate 1967c478bd9Sstevel@tonic-gate /* 1977c478bd9Sstevel@tonic-gate * schizo ECC UE AFSR bit definitions: 1987c478bd9Sstevel@tonic-gate */ 1997c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_ERRPNDG 0x0300000000000000ull 2007c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_MASK 0x000003ff00000000ull 2017c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_MASK_SHIFT 32 2027c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_QW_OFFSET 0x00000000C0000000ull 2037c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT 30 2047c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_AGENT_MID 0x000000001f000000ull 2057c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_AGENT_MID_SHIFT 24 2067c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_PARTIAL 0x0000000000800000ull 2077c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_OWNED_IN 0x0000000000400000ull 2087c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_MTAG_SYND 0x00000000000f0000ull 2097c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_MTAG_SYND_SHIFT 16 2107c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_MTAG 0x000000000000e000ull 2117c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_MTAG_SHIFT 13 2127c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_SYND 0x00000000000001ffull 2137c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_UE_AFSR_SYND_SHIFT 0 2147c478bd9Sstevel@tonic-gate 2157c478bd9Sstevel@tonic-gate /* 2167c478bd9Sstevel@tonic-gate * schizo ECC CE AFSR bit definitions: 2177c478bd9Sstevel@tonic-gate */ 2187c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_ERRPNDG 0x0300000000000000ull 2197c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_MASK 0x000003ff00000000ull 2207c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_MASK_SHIFT 32 2217c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_QW_OFFSET 0x00000000C0000000ull 2227c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT 30 2237c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_AGENT_MID 0x000000001f000000ull 2247c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_AGENT_MID_SHIFT 24 2257c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_PARTIAL 0x0000000000800000ull 2267c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_OWNED_IN 0x0000000000400000ull 2277c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_MTAG_SYND 0x00000000000f0000ull 2287c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_MTAG_SYND_SHIFT 16 2297c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_MTAG 0x000000000000e000ull 2307c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_MTAG_SHIFT 13 2317c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_SYND 0x00000000000001ffull 2327c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_CE_AFSR_SYND_SHIFT 0 2337c478bd9Sstevel@tonic-gate 2347c478bd9Sstevel@tonic-gate /* 2357c478bd9Sstevel@tonic-gate * schizo ECC UE/CE AFAR bit definitions: 2367c478bd9Sstevel@tonic-gate */ 2377c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_IO_TXN 0x0000080000000000ull 2387c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_MASK 0x0000078000000000ull 2397c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_UPA64S 0x0000078000000000ull 2407c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_NL_REG 0x0000040000000000ull 2417c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_NL 0x0000050000000000ull 2427c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_NL_ALT 0x0000051000000000ull 2437c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_PCIA_REG 0x0000020000000000ull 2447c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_PCIA_MEM 0x0000030000000000ull 2457c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO 0x0000031000000000ull 2467c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_PCIB_REG 0x0000000000000000ull 2477c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_PCIB_MEM 0x0000010000000000ull 2487c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO 0x0000011000000000ull 2497c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS 0x0000060000000000ull 2507c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_PIOW_ADDR_MASK 0x0000000fffffffffull 2517c478bd9Sstevel@tonic-gate #define SCHIZO_ECC_AFAR_ADDR_MASK 0x000007ffffffffffull 2527c478bd9Sstevel@tonic-gate 2537c478bd9Sstevel@tonic-gate /* 2547c478bd9Sstevel@tonic-gate * schizo pci control register bits: 2557c478bd9Sstevel@tonic-gate */ 2567c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_BUS_UNUSABLE (1ull << 63) 2577c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_PCI_DTO_ERR (1ull << 62) 2587c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_DTO_INT_EN (1ull << 61) 2597c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_ERR_SLOT_LOCK (1ull << 51) 2607c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_ERR_SLOT (7ull << 48) 2617c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT 48 2627c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_PCI_TTO_ERR (1ull << 38) 2637c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_PCI_RTRY_ERR (1ull << 37) 2647c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_PCI_MMU_ERR (1ull << 36) 2657c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_PEN_RD_MLTPL (1ull << 30) 2667c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_PEN_RD_ONE (1ull << 29) 2677c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_PEN_RD_LINE (1ull << 28) 2687c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_FRC_TRGT_ABRT (1ull << 27) 2697c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_FRC_TRGT_RTRY (1ull << 26) 2707c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_PTO (3ull << 24) 2717c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_PTO_SHIFT 24 2727c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT (3ull << 21) 2737c478bd9Sstevel@tonic-gate #define TOMATILLO_PCI_CTRL_TRGT_RW_STL_WT_SHIFT 21 2747c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_MMU_INT_EN (1ull << 19) 2757c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_SBH_INT_EN (1ull << 18) 2767c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_ERR_INT_EN (1ull << 17) 2777c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_ARB_PARK (1ull << 16) 2787c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_RST (1ull << 8) 2797c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_ARB_EN_MASK 0xffull 2807c478bd9Sstevel@tonic-gate 2817c478bd9Sstevel@tonic-gate #define XMITS10_PCI_CTRL_ARB_EN_MASK 0x0full 2827c478bd9Sstevel@tonic-gate #define XMITS_PCI_CTRL_X_MODE (0x1ull << 32) 2837c478bd9Sstevel@tonic-gate #define XMITS_PCI_CTRL_X_ERRINT_EN (0x1ull << 20) 2847c478bd9Sstevel@tonic-gate #define XMITS_PCI_CTRL_DMA_WR_PERR (0x1ull << 51) 2857c478bd9Sstevel@tonic-gate 2867c478bd9Sstevel@tonic-gate /* 2877c478bd9Sstevel@tonic-gate * schizo PCI asynchronous fault status register bit definitions: 2887c478bd9Sstevel@tonic-gate */ 2897c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_PE_SHIFT 58 2907c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_SE_SHIFT 52 2917c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_E_MA 0x0000000000000020ull 2927c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_E_TA 0x0000000000000010ull 2937c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_E_RTRY 0x0000000000000008ull 2947c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_E_PERR 0x0000000000000004ull 2957c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_E_TTO 0x0000000000000002ull 2967c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_E_UNUSABLE 0x0000000000000001ull 2977c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_E_MASK 0x000000000000003full 2987c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_DWORDMASK 0x0000030000000000ull 2997c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_DWORDMASK_SHIFT 40 3007c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_BYTEMASK 0x000000ff00000000ull 3017c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_BYTEMASK_SHIFT 32 3027c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_BLK 0x0000000080000000ull 3037c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_CONF_SPACE 0x0000000040000000ull 3047c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_MEM_SPACE 0x0000000020000000ull 3057c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_AFSR_IO_SPACE 0x0000000010000000ull 3067c478bd9Sstevel@tonic-gate 3077c478bd9Sstevel@tonic-gate /* Schizo/Xmits control block Safari Error log bits */ 3087c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_BAD_CMD (0x1ull << 62) 3097c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_SSM_DIS (0x1ull << 61) 3107c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_BAD_CMD_PCIA (0x1ull << 60) 3117c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_BAD_CMD_PCIB (0x1ull << 59) 3127c478bd9Sstevel@tonic-gate #define XMITS_CB_ELOG_PAR_ERR_INT_PCIB (0x1ull << 19) 3137c478bd9Sstevel@tonic-gate #define XMITS_CB_ELOG_PAR_ERR_INT_PCIA (0x1ull << 18) 3147c478bd9Sstevel@tonic-gate #define XMITS_CB_ELOG_PAR_ERR_INT_SAF (0x1ull << 17) 3157c478bd9Sstevel@tonic-gate #define XMITS_CB_ELOG_PLL_ERR_PCIB (0x1ull << 16) 3167c478bd9Sstevel@tonic-gate #define XMITS_CB_ELOG_PLL_ERR_PCIA (0x1ull << 15) 3177c478bd9Sstevel@tonic-gate #define XMITS_CB_ELOG_PLL_ERR_SAF (0x1ull << 14) 3187c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_CPU1_PAR_SINGLE (0x1ull << 13) 3197c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_CPU1_PAR_BIDI (0x1ull << 12) 3207c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_CPU0_PAR_SINGLE (0x1ull << 11) 3217c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_CPU0_PAR_BIDI (0x1ull << 10) 3227c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_SAF_CIQ_TO (0x1ull << 9) 3237c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_SAF_LPQ_TO (0x1ull << 8) 3247c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_SAF_SFPQ_TO (0x1ull << 7) 3257c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_SAF_UFPQ_TO (0x1ull << 6) 3267c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_ADDR_PAR_ERR (0x1ull << 5) 3277c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_UNMAP_ERR (0x1ull << 4) 3287c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_BUS_ERR (0x1ull << 2) 3297c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_TO_ERR (0x1ull << 1) 3307c478bd9Sstevel@tonic-gate #define SCHIZO_CB_ELOG_DSTAT_ERR 0x1ull 3317c478bd9Sstevel@tonic-gate 3327c478bd9Sstevel@tonic-gate /* Used for the tomatillo micro tlb bug. errata #82 */ 3337c478bd9Sstevel@tonic-gate #define SCHIZO_VPN_MASK ((1 << 19) - 1) 3347c478bd9Sstevel@tonic-gate 3357c478bd9Sstevel@tonic-gate /* Tomatillo control block JBUS error log bits */ 3367c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR_GR (0x1ull << 21) 3377c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR_PCI (0x1ull << 20) 3387c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR_RD (0x1ull << 19) 3397c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDS (0x1ull << 17) 3407c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA (0x1ull << 16) 3417c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR_OWN (0x1ull << 15) 3427c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR_RDO (0x1ull << 14) 3437c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR (0x1ull << 13) 3447c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_CTL_PAR_ERR (0x1ull << 12) 3457c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_SNOOP_ERR (0x1ull << 11) 3467c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_ILL_BYTE_EN (0x1ull << 10) 3477c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_ILL_COH_IN (0x1ull << 8) 3487c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR (0x1ull << 6) 3497c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_ELOG_TO_EXP_ERR (0x1ull << 3) 3507c478bd9Sstevel@tonic-gate 3517c478bd9Sstevel@tonic-gate /* Tomatillo control block JBUS control/status bits */ 3527c478bd9Sstevel@tonic-gate #define TOMATILLO_CB_CSR_CTRL_PERR_GEN (0x1ull << 29) 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_AFSR_P_SC_ERR (0x1ull << 51) 3557c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_AFSR_S_SC_ERR (0x1ull << 50) 3567c478bd9Sstevel@tonic-gate 3577c478bd9Sstevel@tonic-gate #define XMITS_PCIX_MSG_CLASS_MASK 0xf00 3587c478bd9Sstevel@tonic-gate #define XMITS_PCIX_MSG_INDEX_MASK 0xff 3597c478bd9Sstevel@tonic-gate #define XMITS_PCIX_MSG_MASK \ 3607c478bd9Sstevel@tonic-gate (XMITS_PCIX_MSG_CLASS_MASK | XMITS_PCIX_MSG_INDEX_MASK) 3617c478bd9Sstevel@tonic-gate 3627c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_P_MSG_SHIFT 16 3637c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_S_MSG_SHIFT 4 3647c478bd9Sstevel@tonic-gate 3657c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_PRIERR(afsr) \ 3667c478bd9Sstevel@tonic-gate (afsr >> SCHIZO_PCI_AFSR_PE_SHIFT & SCHIZO_PCI_AFSR_E_MASK) 3677c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_SECERR(afsr) \ 3687c478bd9Sstevel@tonic-gate (afsr >> SCHIZO_PCI_AFSR_SE_SHIFT & SCHIZO_PCI_AFSR_E_MASK) 3697c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_BYTEMASK(afsr) \ 3707c478bd9Sstevel@tonic-gate ((afsr & SCHIZO_PCI_AFSR_BYTEMASK) >> SCHIZO_PCI_AFSR_BYTEMASK_SHIFT) 3717c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_DWORDMASK(afsr) \ 3727c478bd9Sstevel@tonic-gate ((afsr & SCHIZO_PCI_AFSR_DWORDMASK) >> \ 3737c478bd9Sstevel@tonic-gate SCHIZO_PCI_AFSR_DWORDMASK_SHIFT) 3747c478bd9Sstevel@tonic-gate 3757c478bd9Sstevel@tonic-gate /* 376810a4a70Sdanice * XMITS Upper Retry Counter Register (bits 15:0) 377810a4a70Sdanice */ 378810a4a70Sdanice #define XMITS_UPPER_RETRY_MASK 0xFFFF 379810a4a70Sdanice 380810a4a70Sdanice /* 3817c478bd9Sstevel@tonic-gate * XMITS PCI-X Diagnostic Register bit definitions 3827c478bd9Sstevel@tonic-gate */ 3837c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_DIS_FAIR (0x1ull << 19) 3847c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_CRCQ_VALID (0x1ull << 18) 3857c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_SRCQ_VALID_SHIFT 10 3867c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_SRCQ_ONE (0x1ull << 9) 3877c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_CRCQ_FLUSH (0x1ull << 8) 3887c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_SRCQ_FLUSH_SHIFT 0 38957026b47Sdanice #define XMITS_PCI_X_DIAG_BUGCNTL_MASK 0xFFFF /* bits 47:32 */ 39057026b47Sdanice #define XMITS_PCI_X_DIAG_BUGCNTL_SHIFT 32 3917c478bd9Sstevel@tonic-gate 3927c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_DIAG_SRCQ_MASK 0xff 3937c478bd9Sstevel@tonic-gate 3947c478bd9Sstevel@tonic-gate /* 3957c478bd9Sstevel@tonic-gate * XMITS PCI-X Error Status Register bit definitions 3967c478bd9Sstevel@tonic-gate */ 3977c478bd9Sstevel@tonic-gate 3987c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_STATUS_PE_SHIFT 58 3997c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_STATUS_SE_SHIFT 50 4007c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_STATUS_E_MASK 0x3f 4017c478bd9Sstevel@tonic-gate #define XMITS_PCI_X_STATUS_PFAR_MASK 0xffffffff 4027c478bd9Sstevel@tonic-gate #define XMITS_PCIX_STAT_SC_DSCRD 0x20ull 4037c478bd9Sstevel@tonic-gate #define XMITS_PCIX_STAT_SC_TTO 0x10ull 404*b5d991cdSdanice /* 405*b5d991cdSdanice * As a workaround for an XMITS ASIC bug, the following PCI-X errors are 406*b5d991cdSdanice * assigned new bit positions within the PCI-X Error Status Register to 407*b5d991cdSdanice * match what is actually implemented in the XMITS ASIC: 408*b5d991cdSdanice * 409*b5d991cdSdanice * Spec New 410*b5d991cdSdanice * Error Bit Position Bit Position 411*b5d991cdSdanice * -------------------- ------------ ------------ 412*b5d991cdSdanice * XMITS_PCIX_STAT_SMMU 0x8ull 0x4ull 413*b5d991cdSdanice * XMITS_PCIX_STAT_SDSTAT 0x4ull 0x8ull 414*b5d991cdSdanice * XMITS_PCIX_STAT_CMMU 0x2ull 0x1ull 415*b5d991cdSdanice * XMITS_PCIX_STAT_CDSTAT 0x1ull 0x2ull 416*b5d991cdSdanice * 417*b5d991cdSdanice */ 418*b5d991cdSdanice #define XMITS_PCIX_STAT_SMMU 0x4ull 419*b5d991cdSdanice #define XMITS_PCIX_STAT_SDSTAT 0x8ull 420*b5d991cdSdanice #define XMITS_PCIX_STAT_CMMU 0x1ull 421*b5d991cdSdanice #define XMITS_PCIX_STAT_CDSTAT 0x2ull 422*b5d991cdSdanice 4237c478bd9Sstevel@tonic-gate #define XMITS_PCIX_STAT_SERR_ON_PERR (1ull << 32) 4247c478bd9Sstevel@tonic-gate #define XMITS_PCIX_STAT_PERR_RECOV_INT_EN (1ull << 33) 4257c478bd9Sstevel@tonic-gate #define XMITS_PCIX_STAT_PERR_RECOV_INT (1ull << 34) 4267c478bd9Sstevel@tonic-gate 4277c478bd9Sstevel@tonic-gate /* 4287c478bd9Sstevel@tonic-gate * PCI-X Message Classes and Indexes 4297c478bd9Sstevel@tonic-gate */ 4307c478bd9Sstevel@tonic-gate #define PCIX_CLASS_WRITE_COMPLETION 0x000 4317c478bd9Sstevel@tonic-gate #define PCIX_WRITE_COMPLETION_NORMAL 0x00 4327c478bd9Sstevel@tonic-gate 4337c478bd9Sstevel@tonic-gate #define PCIX_CLASS_BRIDGE 0x100 4347c478bd9Sstevel@tonic-gate #define PCIX_BRIDGE_MASTER_ABORT 0x00 4357c478bd9Sstevel@tonic-gate #define PCIX_BRIDGE_TARGET_ABORT 0x01 4367c478bd9Sstevel@tonic-gate #define PCIX_BRIDGE_WRITE_DATA_PARITY 0x02 4377c478bd9Sstevel@tonic-gate 4387c478bd9Sstevel@tonic-gate #define PCIX_CLASS_CPLT 0x200 4397c478bd9Sstevel@tonic-gate #define PCIX_CPLT_OUT_OF_RANGE 0x00 4407c478bd9Sstevel@tonic-gate #define PCIX_CPLT_SPLIT_WRITE_DATA 0x01 4417c478bd9Sstevel@tonic-gate #define XMITS_CPLT_NO_ERROR 0x80 4427c478bd9Sstevel@tonic-gate #define XMITS_CPLT_STREAM_DSTAT 0x81 4437c478bd9Sstevel@tonic-gate #define XMITS_CPLT_STREAM_MMU 0x82 4447c478bd9Sstevel@tonic-gate #define XMITS_CPLT_CONSIST_DSTAT 0x85 4457c478bd9Sstevel@tonic-gate #define XMITS_CPLT_CONSIST_MMU 0x86 4467c478bd9Sstevel@tonic-gate 4477c478bd9Sstevel@tonic-gate #define PCIX_NO_CLASS 0x999 4487c478bd9Sstevel@tonic-gate #define PCIX_MULTI_ERR 1 4497c478bd9Sstevel@tonic-gate #define PCIX_SINGLE_ERR 0 4507c478bd9Sstevel@tonic-gate 4517c478bd9Sstevel@tonic-gate #define PBM_PCIX_TO_PRIERR(pcix_stat) \ 4527c478bd9Sstevel@tonic-gate (pcix_stat >> XMITS_PCI_X_STATUS_PE_SHIFT & XMITS_PCI_X_STATUS_E_MASK) 4537c478bd9Sstevel@tonic-gate #define PBM_PCIX_TO_SECERR(pcix_stat) \ 4547c478bd9Sstevel@tonic-gate (pcix_stat >> XMITS_PCI_X_STATUS_SE_SHIFT & XMITS_PCI_X_STATUS_E_MASK) 4557c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_PRISPLIT(afsr) \ 4567c478bd9Sstevel@tonic-gate ((afsr >> XMITS_PCI_X_P_MSG_SHIFT) & XMITS_PCIX_MSG_MASK) 4577c478bd9Sstevel@tonic-gate #define PBM_AFSR_TO_SECSPLIT(afsr) \ 4587c478bd9Sstevel@tonic-gate ((afsr >> XMITS_PCI_X_S_MSG_SHIFT) & XMITS_PCIX_MSG_MASK) 4597c478bd9Sstevel@tonic-gate 4607c478bd9Sstevel@tonic-gate #define PCIX_ERRREG_OFFSET (XMITS_PCI_X_ERROR_STATUS_REG_OFFSET -\ 4617c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_REG_OFFSET) 4627c478bd9Sstevel@tonic-gate 4637c478bd9Sstevel@tonic-gate /* 4647c478bd9Sstevel@tonic-gate * Nested message structure to allow for storing all the PCI-X 4657c478bd9Sstevel@tonic-gate * split completion messages in tabular form. 4667c478bd9Sstevel@tonic-gate */ 4677c478bd9Sstevel@tonic-gate typedef struct pcix_err_msg_rec { 4687c478bd9Sstevel@tonic-gate uint32_t msg_key; 4697c478bd9Sstevel@tonic-gate char *msg_class; 4707c478bd9Sstevel@tonic-gate char *msg_str; 4717c478bd9Sstevel@tonic-gate } pcix_err_msg_rec_t; 4727c478bd9Sstevel@tonic-gate 4737c478bd9Sstevel@tonic-gate typedef struct pcix_err_tbl { 4747c478bd9Sstevel@tonic-gate uint32_t err_class; 4757c478bd9Sstevel@tonic-gate uint32_t err_rec_num; 4767c478bd9Sstevel@tonic-gate pcix_err_msg_rec_t *err_msg_tbl; 4777c478bd9Sstevel@tonic-gate } pcix_err_tbl_t; 4787c478bd9Sstevel@tonic-gate 4797c478bd9Sstevel@tonic-gate 4807c478bd9Sstevel@tonic-gate /* 4817c478bd9Sstevel@tonic-gate * Tomatillo IO Cache CSR bit definitions: 4827c478bd9Sstevel@tonic-gate */ 4837c478bd9Sstevel@tonic-gate 4847c478bd9Sstevel@tonic-gate #define TOMATILLO_WRT_PEN (1ull << 19) 4857c478bd9Sstevel@tonic-gate #define TOMATILLO_NC_PEN_RD_MLTPL (1ull << 18) 4867c478bd9Sstevel@tonic-gate #define TOMATILLO_NC_PEN_RD_ONE (1ull << 17) 4877c478bd9Sstevel@tonic-gate #define TOMATILLO_NC_PEN_RD_LINE (1ull << 16) 4887c478bd9Sstevel@tonic-gate #define TOMATILLO_PLEN_RD_MTLPL (3ull << 14) 4897c478bd9Sstevel@tonic-gate #define TOMATILLO_PLEN_RD_ONE (3ull << 12) 4907c478bd9Sstevel@tonic-gate #define TOMATILLO_PLEN_RD_LINE (3ull << 10) 4917c478bd9Sstevel@tonic-gate #define TOMATILLO_POFFSET_SHIFT 3 4927c478bd9Sstevel@tonic-gate #define TOMATILLO_POFFSET (0x7full << TOMATILLO_POFFSET_SHIFT) 4937c478bd9Sstevel@tonic-gate #define TOMATILLO_C_PEN_RD_MLTPL (1ull << 2) 4947c478bd9Sstevel@tonic-gate #define TOMATILLO_C_PEN_RD_ONE (1ull << 1) 4957c478bd9Sstevel@tonic-gate #define TOMATILLO_C_PEN_RD_LINE (1ull << 0) 4967c478bd9Sstevel@tonic-gate 4977c478bd9Sstevel@tonic-gate /* 4987c478bd9Sstevel@tonic-gate * schizo PCI diagnostic register bit definitions: 4997c478bd9Sstevel@tonic-gate */ 5007c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_DIAG_DIS_RTRY_ARB 0x0000000000000080ull 5017c478bd9Sstevel@tonic-gate 5027c478bd9Sstevel@tonic-gate /* 5037c478bd9Sstevel@tonic-gate * schizo IOMMU TLB TAG diagnostic register bits 5047c478bd9Sstevel@tonic-gate */ 5057c478bd9Sstevel@tonic-gate #define TLBTAG_CONTEXT_SHIFT 25 5067c478bd9Sstevel@tonic-gate #define TLBTAG_ERRSTAT_SHIFT 23 5077c478bd9Sstevel@tonic-gate #define TLBTAG_CONTEXT_BITS (0xfffull << TLBTAG_CONTEXT_SHIFT) 5087c478bd9Sstevel@tonic-gate #define TLBTAG_ERRSTAT_BITS (0x3ull << TLBTAG_ERRSTAT_SHIFT) 5097c478bd9Sstevel@tonic-gate #define TLBTAG_ERR_BIT (0x1ull << 22) 5107c478bd9Sstevel@tonic-gate #define TLBTAG_WRITABLE_BIT (0x1ull << 21) 5117c478bd9Sstevel@tonic-gate #define TLBTAG_STREAM_BIT (0x1ull << 20) 5127c478bd9Sstevel@tonic-gate #define TLBTAG_PGSIZE_BIT (0x1ull << 19) 5137c478bd9Sstevel@tonic-gate #define TLBTAG_PCIVPN_BITS 0x7ffffull 5147c478bd9Sstevel@tonic-gate 5157c478bd9Sstevel@tonic-gate #define TLBTAG_ERRSTAT_PROT 0 5167c478bd9Sstevel@tonic-gate #define TLBTAG_ERRSTAT_INVALID 1 5177c478bd9Sstevel@tonic-gate #define TLBTAG_ERRSTAT_TIMEOUT 2 5187c478bd9Sstevel@tonic-gate #define TLBTAG_ERRSTAT_ECCUE 3 5197c478bd9Sstevel@tonic-gate 5207c478bd9Sstevel@tonic-gate /* 5217c478bd9Sstevel@tonic-gate * schizo IOMMU TLB Data RAM diagnostic register bits 5227c478bd9Sstevel@tonic-gate */ 5237c478bd9Sstevel@tonic-gate #define TLBDATA_VALID_BIT (0x1ull << 32) 5247c478bd9Sstevel@tonic-gate #define TLBDATA_CACHE_BIT (0x1ull << 30) 5257c478bd9Sstevel@tonic-gate #define TLBDATA_MEMPA_BITS ((0x1ull << 30) - 1) 5267c478bd9Sstevel@tonic-gate 5277c478bd9Sstevel@tonic-gate extern uint_t cb_buserr_intr(caddr_t a); 5287c478bd9Sstevel@tonic-gate 5297c478bd9Sstevel@tonic-gate /* 5307c478bd9Sstevel@tonic-gate * pbm_cdma_flag(schizo only): consistent dma sync handshake 5317c478bd9Sstevel@tonic-gate */ 5327c478bd9Sstevel@tonic-gate #define PBM_CDMA_DONE 0xcc /* arbitrary pattern set by interrupt handler */ 5337c478bd9Sstevel@tonic-gate #define PBM_CDMA_PEND 0x55 /* arbitrary pattern set by sync requester */ 5347c478bd9Sstevel@tonic-gate #define PBM_CDMA_INO_BASE 0x35 /* ino can be used for cdma sync */ 5357c478bd9Sstevel@tonic-gate 5367c478bd9Sstevel@tonic-gate /* 5377c478bd9Sstevel@tonic-gate * Estar control bit for schizo estar reg 5387c478bd9Sstevel@tonic-gate */ 5397c478bd9Sstevel@tonic-gate #define SCHIZO_PCI_CTRL_BUS_SPEED 0x0000000000000001ull 5407c478bd9Sstevel@tonic-gate 5417c478bd9Sstevel@tonic-gate #define PCI_CMN_ID(chip_type, id) \ 5427c478bd9Sstevel@tonic-gate ((chip_type) == PCI_CHIP_TOMATILLO ? ((id) >> 1) << 1 : (id)) 5437c478bd9Sstevel@tonic-gate #define PCI_ID_TO_IGN(pci_id) ((pci_ign_t)((pci_id) & 0x1f)) 5447c478bd9Sstevel@tonic-gate #define PCI_ID_TO_NODEID(pci_id) ((cb_nid_t)((pci_id) >> PCI_IGN_BITS)) 5457c478bd9Sstevel@tonic-gate 5467c478bd9Sstevel@tonic-gate #define PCI_BRIDGE_TYPE(cmn_p) \ 5477c478bd9Sstevel@tonic-gate (((cmn_p->pci_chip_id >> 16) == PCI_CHIP_SCHIZO) ? PCI_SCHIZO : \ 5487c478bd9Sstevel@tonic-gate ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_TOMATILLO) ? PCI_TOMATILLO : \ 5497c478bd9Sstevel@tonic-gate ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_XMITS) ? PCI_XMITS : "") 5507c478bd9Sstevel@tonic-gate /* 5517c478bd9Sstevel@tonic-gate * Tomatillo only 5527c478bd9Sstevel@tonic-gate */ 5537c478bd9Sstevel@tonic-gate #define NBIGN(ib_p) ((ib_p)->ib_ign ^ 1) 5547c478bd9Sstevel@tonic-gate #define IB_INO_TO_NBMONDO(ib_p, ino) IB_IGN_TO_MONDO(NBIGN(ib_p), ino) 5557c478bd9Sstevel@tonic-gate 5567c478bd9Sstevel@tonic-gate /* 5577c478bd9Sstevel@tonic-gate * Mask to tell which PCI Side we are on 5587c478bd9Sstevel@tonic-gate */ 5597c478bd9Sstevel@tonic-gate #define PCI_SIDE_ADDR_MASK 0x100000ull 5607c478bd9Sstevel@tonic-gate 5617c478bd9Sstevel@tonic-gate /* 5627c478bd9Sstevel@tonic-gate * Offset from Schizo Base of Schizo CSR Base 5637c478bd9Sstevel@tonic-gate */ 5647c478bd9Sstevel@tonic-gate #define PBM_CTRL_OFFSET 0x410000ull 5657c478bd9Sstevel@tonic-gate 56649f91442Ssuha /* 56749f91442Ssuha * The following macro defines the 42-bit bus width support for SAFARI bus 56849f91442Ssuha * and JBUS in DVMA and iommu bypass transfers: 56949f91442Ssuha */ 57049f91442Ssuha 57149f91442Ssuha #define SAFARI_JBUS_IOMMU_BYPASS_END 0xFFFC03FFFFFFFFFFull 57249f91442Ssuha 5737c478bd9Sstevel@tonic-gate #ifdef __cplusplus 5747c478bd9Sstevel@tonic-gate } 5757c478bd9Sstevel@tonic-gate #endif 5767c478bd9Sstevel@tonic-gate 5777c478bd9Sstevel@tonic-gate #endif /* _SYS_PCISCH_H */ 578