1*4df55fdeSJanie Lu /* 2*4df55fdeSJanie Lu * CDDL HEADER START 3*4df55fdeSJanie Lu * 4*4df55fdeSJanie Lu * The contents of this file are subject to the terms of the 5*4df55fdeSJanie Lu * Common Development and Distribution License (the "License"). 6*4df55fdeSJanie Lu * You may not use this file except in compliance with the License. 7*4df55fdeSJanie Lu * 8*4df55fdeSJanie Lu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*4df55fdeSJanie Lu * or http://www.opensolaris.org/os/licensing. 10*4df55fdeSJanie Lu * See the License for the specific language governing permissions 11*4df55fdeSJanie Lu * and limitations under the License. 12*4df55fdeSJanie Lu * 13*4df55fdeSJanie Lu * When distributing Covered Code, include this CDDL HEADER in each 14*4df55fdeSJanie Lu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*4df55fdeSJanie Lu * If applicable, add the following below this CDDL HEADER, with the 16*4df55fdeSJanie Lu * fields enclosed by brackets "[]" replaced with your own identifying 17*4df55fdeSJanie Lu * information: Portions Copyright [yyyy] [name of copyright owner] 18*4df55fdeSJanie Lu * 19*4df55fdeSJanie Lu * CDDL HEADER END 20*4df55fdeSJanie Lu */ 21*4df55fdeSJanie Lu 22*4df55fdeSJanie Lu /* 23*4df55fdeSJanie Lu * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24*4df55fdeSJanie Lu * Use is subject to license terms. 25*4df55fdeSJanie Lu */ 26*4df55fdeSJanie Lu 27*4df55fdeSJanie Lu #ifndef _RFIOSPC_TABLES_H 28*4df55fdeSJanie Lu #define _RFIOSPC_TABLES_H 29*4df55fdeSJanie Lu 30*4df55fdeSJanie Lu /* 31*4df55fdeSJanie Lu * Table definitions for the RF IOS performance counters. 32*4df55fdeSJanie Lu * 33*4df55fdeSJanie Lu * Each table consists of one or more groups of counters. 34*4df55fdeSJanie Lu * 35*4df55fdeSJanie Lu * A counter group will have a name (used by busstat as the kstat "module" 36*4df55fdeSJanie Lu * name), have its own set of kstats, and a common event select register. 37*4df55fdeSJanie Lu * A group is represented as an iospc_grp_t. 38*4df55fdeSJanie Lu * 39*4df55fdeSJanie Lu * Each counter is represented by an iospc_cntr_t. Each has its own register 40*4df55fdeSJanie Lu * offset (or address), bits for the data it represents, plus an associated 41*4df55fdeSJanie Lu * register for zeroing it. 42*4df55fdeSJanie Lu * 43*4df55fdeSJanie Lu * All registers for iospc are 64 bit, but a size field can be entered into this 44*4df55fdeSJanie Lu * structure if registers sizes vary for other implementations (as if this code 45*4df55fdeSJanie Lu * is leveraged for a future driver). 46*4df55fdeSJanie Lu * 47*4df55fdeSJanie Lu * A select register is represented by an iospc_regsel_t. This defines the 48*4df55fdeSJanie Lu * offset or address, and an array of fields which define the events for each 49*4df55fdeSJanie Lu * counter it services. All counters need to have an entry in the fields array 50*4df55fdeSJanie Lu * even if they don't have any representation in a select register. Please see 51*4df55fdeSJanie Lu * the explanation of the events array (below) for more information. Counters 52*4df55fdeSJanie Lu * without representation in a select register can specify their (non-existant) 53*4df55fdeSJanie Lu * select register field with mask NONPROG_DUMMY_MASK and offset 54*4df55fdeSJanie Lu * NONPROG_DUMMY_OFF. 55*4df55fdeSJanie Lu * 56*4df55fdeSJanie Lu * This implementation supports only one select register per group. If more 57*4df55fdeSJanie Lu * are needed (e.g. if this implementation is used as a template for another 58*4df55fdeSJanie Lu * device which has multiple select registers per group) the data structures can 59*4df55fdeSJanie Lu * easily be changed to support an array of them. Add an array index in the 60*4df55fdeSJanie Lu * counter structure to associate that counter with a particular select 61*4df55fdeSJanie Lu * register, and add a field for the number of select registers in the group 62*4df55fdeSJanie Lu * structure. 63*4df55fdeSJanie Lu * 64*4df55fdeSJanie Lu * Each counter has an array of programmable events associated with it, even if 65*4df55fdeSJanie Lu * it is not programmable. This array is a series of name/value pairs defined 66*4df55fdeSJanie Lu * by iospc_event_t. The value is the event value loaded into the select 67*4df55fdeSJanie Lu * register to select that event for that counter. The last entry in the array 68*4df55fdeSJanie Lu * is always an entry with a bitmask of LSB-aligned bits of that counter's 69*4df55fdeSJanie Lu * select register's field's width; it is usually called the CLEAR_PIC entry. 70*4df55fdeSJanie Lu * CLEAR_PIC entries are not shown to the user. 71*4df55fdeSJanie Lu * 72*4df55fdeSJanie Lu * Note that counters without programmable events still need to define a 73*4df55fdeSJanie Lu * (small) events array with at least CLEAR_PIC and a single event, so that 74*4df55fdeSJanie Lu * event's name can display in busstat output. The CLEAR_PIC entry of 75*4df55fdeSJanie Lu * nonprogrammable counters can have a value of NONPROG_DUMMY_MASK. 76*4df55fdeSJanie Lu */ 77*4df55fdeSJanie Lu 78*4df55fdeSJanie Lu #ifdef __cplusplus 79*4df55fdeSJanie Lu extern "C" { 80*4df55fdeSJanie Lu #endif 81*4df55fdeSJanie Lu 82*4df55fdeSJanie Lu #include <sys/types.h> 83*4df55fdeSJanie Lu #include <sys/kstat.h> 84*4df55fdeSJanie Lu 85*4df55fdeSJanie Lu /* RF IOS specific definitions. */ 86*4df55fdeSJanie Lu 87*4df55fdeSJanie Lu /* 88*4df55fdeSJanie Lu * Event bitmask definitions for all groups. 89*4df55fdeSJanie Lu */ 90*4df55fdeSJanie Lu #define RFIOS_IMU_CTR_EVT_MASK 0xffull 91*4df55fdeSJanie Lu #define RFIOS_IMU_CTR_0_EVT_OFF 0 92*4df55fdeSJanie Lu #define RFIOS_IMU_CTR_1_EVT_OFF 8 93*4df55fdeSJanie Lu 94*4df55fdeSJanie Lu #define RFIOS_ATU_CTR_EVT_MASK 0xffull 95*4df55fdeSJanie Lu #define RFIOS_ATU_CTR_0_EVT_OFF 0 96*4df55fdeSJanie Lu #define RFIOS_ATU_CTR_1_EVT_OFF 8 97*4df55fdeSJanie Lu 98*4df55fdeSJanie Lu #define RFIOS_NPU_CTR_EVT_MASK 0xffull 99*4df55fdeSJanie Lu #define RFIOS_NPU_CTR_0_EVT_OFF 0 100*4df55fdeSJanie Lu #define RFIOS_NPU_CTR_1_EVT_OFF 8 101*4df55fdeSJanie Lu 102*4df55fdeSJanie Lu #define RFIOS_PEX_CTR_EVT_MASK 0xffull 103*4df55fdeSJanie Lu #define RFIOS_PEX_CTR_0_EVT_OFF 0 104*4df55fdeSJanie Lu #define RFIOS_PEX_CTR_1_EVT_OFF 8 105*4df55fdeSJanie Lu 106*4df55fdeSJanie Lu #define RFIOS_PEU_CTR_EVT_MASK 0x7full 107*4df55fdeSJanie Lu #define RFIOS_PEU_CTR_0_EVT_OFF 0 108*4df55fdeSJanie Lu #define RFIOS_PEU_CTR_1_EVT_OFF 32 109*4df55fdeSJanie Lu 110*4df55fdeSJanie Lu /* 111*4df55fdeSJanie Lu * Definitions of the different types of events. 112*4df55fdeSJanie Lu * 113*4df55fdeSJanie Lu * The first part says which registers these events are for. 114*4df55fdeSJanie Lu * For example, IMU01 means the IMU performance counters 0 and 1 115*4df55fdeSJanie Lu */ 116*4df55fdeSJanie Lu 117*4df55fdeSJanie Lu /* String sought by busstat to locate the event field width "event" entry. */ 118*4df55fdeSJanie Lu #define COMMON_S_CLEAR_PIC "clear_pic" 119*4df55fdeSJanie Lu 120*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_NONE "event_none" 121*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_CLK "clock_cyc" 122*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_TOTAL_MSIX "total_msix" 123*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_IOS_MSI "ios_msi" 124*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_PCIE_MSIX "pcie_msix" 125*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_PCIE_MSGS "pcie_msgs" 126*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_FILTERED_MSIX "filtered_msix" 127*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_EQ_WR "eq_write" 128*4df55fdeSJanie Lu #define RFIOS_IMU01_S_EVT_MONDOS "mondos" 129*4df55fdeSJanie Lu 130*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_NONE 0x0 131*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_CLK 0x1 132*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_TOTAL_MSIX 0x2 133*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_IOS_MSI 0x3 134*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_PCIE_MSIX 0x4 135*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_PCIE_MSGS 0x5 136*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_FILTERED_MSIX 0x6 137*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_EQ_WR 0x7 138*4df55fdeSJanie Lu #define RFIOS_IMU01_EVT_MONDOS 0x8 139*4df55fdeSJanie Lu 140*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_NONE "event_none" 141*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_CLK "clock_cyc" 142*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_FLOW_CTRL_STALL "flow_ctrl_cyc" 143*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_CLUMP_ACC "clump_accesses" 144*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_CLUMP_MISS "clump_misses" 145*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_CLUMP_RESETS "clump_resets" 146*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_CLUMP_TBL_WALK "clump_table_walk" 147*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_VIRT_ACC "virt_accesses" 148*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_VIRT_MISS "virt_misses" 149*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_VIRT_RESETS "virt_resets" 150*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_VIRT_TBL_WALK "virt_table_walk" 151*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_REAL_ACC "real_accesses" 152*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_REAL_MISS "real_misses" 153*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_REAL_RESETS "real_resets" 154*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_REAL_TBL_WALK "real_table_walk" 155*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_CMD_ERRORS "cmd_errors" 156*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_VIRT_TRANS "virt_trans" 157*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_REAL_TRANS "real_trans" 158*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_PHYS_TRANS "phys_trans" 159*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_STRICT_ORDER_FORCED "str_order_forced" 160*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_RELAX_ORDER_FORCED "relax_order_forced" 161*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_RELAX_ORDER_TLP "relax_order_tlp" 162*4df55fdeSJanie Lu #define RFIOS_ATU01_S_EVT_RELAX_ORDER_TOTAL "relax_order_total" 163*4df55fdeSJanie Lu 164*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_NONE 0x0 165*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_CLK 0x1 166*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_FLOW_CTRL_STALL 0x3 167*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_CLUMP_ACC 0x4 168*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_CLUMP_MISS 0x5 169*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_CLUMP_RESETS 0x6 170*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_CLUMP_TBL_WALK 0x7 171*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_VIRT_ACC 0x8 172*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_VIRT_MISS 0x9 173*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_VIRT_RESETS 0xa 174*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_VIRT_TBL_WALK 0xb 175*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_REAL_ACC 0xc 176*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_REAL_MISS 0xd 177*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_REAL_RESETS 0xe 178*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_REAL_TBL_WALK 0xf 179*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_CMD_ERRORS 0x10 180*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_VIRT_TRANS 0x11 181*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_REAL_TRANS 0x12 182*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_PHYS_TRANS 0x13 183*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_STRICT_ORDER_FORCED 0x14 184*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_RELAX_ORDER_FORCED 0x15 185*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_RELAX_ORDER_TLP 0x16 186*4df55fdeSJanie Lu #define RFIOS_ATU01_EVT_RELAX_ORDER_TOTAL 0x17 187*4df55fdeSJanie Lu 188*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_NONE "event_none" 189*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_CLK "clock_cyc" 190*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ZERO_BYTE_READ "zero_byte_reads" 191*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_DMA_WRITE_LATENCY "write_latency" 192*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_DMA_WRITE_LATENCY_NUM "write_latency_num" 193*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_OSB_FULL_CYCLES "osb_full_cyc" 194*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_DMA_READ_LATENCY "read_latency" 195*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_DMA_READ_LATENCY_NUM "read_latency_num" 196*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_PSB_FULL_CYCLES "psb_full_cyc" 197*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ICB_FULL_CYCLES "icb_full_cyc" 198*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ECB_FULL_CYCLES "ecb_full_cyc" 199*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ATU_CSR_CFG_WRITES "atu_csr_cfg_wrs" 200*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ATU_CSR_CFG_READS "atu_csr_cfg_rds" 201*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ATU_CSR_MEM_WRITES "atu_csr_mem_wrs" 202*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ATU_CSR_MEM_READS "atu_csr_mem_rds" 203*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_IMU_CSR_CFG_WRITES "imu_csr_cfg_wrs" 204*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_IMU_CSR_CFG_READS "imu_csr_cfg_rds" 205*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_IMU_CSR_MEM_WRITES "imu_csr_mem_wrs" 206*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_IMU_CSR_MEM_READS "imu_csr_mem_rds" 207*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_NPU_CSR_CFG_WRITES "npu_csr_cfg_wrs" 208*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_NPU_CSR_CFG_READS "npu_csr_cfg_rds" 209*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_NPU_CSR_MEM_WRITES "npu_csr_mem_wrs" 210*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_NPU_CSR_MEM_READS "npu_csr_mem_rds" 211*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_OTHER_CSR_CFG_WRITES "other_csr_cfg_wrs" 212*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_OTHER_CSR_CFG_READS "other_csr_cfg_rds" 213*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM64_WRITES \ 214*4df55fdeSJanie Lu "other_csr_mem64_wrs" 215*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM64_READS "other_csr_mem64_rds" 216*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM32_WRITES \ 217*4df55fdeSJanie Lu "other_csr_mem32_wrs" 218*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM32_READS "other_csr_mem32_rds" 219*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_IO_SPACE_WRITES "io_space_wrs" 220*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_IO_SPACE_READS "io_space_rds" 221*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_TOTAL_MSI "total_msi" 222*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_ATU_MSI "atu_msi" 223*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_IMU_MSI "imu_msi" 224*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_NPU_MSI "npu_msi" 225*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_RETIRED_TAGS_CTO "retired_tags" 226*4df55fdeSJanie Lu #define RFIOS_NPU01_S_EVT_NO_POSTED_TAGS_CYCYLES \ 227*4df55fdeSJanie Lu "no_posted_tags_cyc" 228*4df55fdeSJanie Lu 229*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_NONE 0 230*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_CLK 1 231*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ZERO_BYTE_READ 2 232*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_DMA_WRITE_LATENCY 3 233*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_DMA_WRITE_LATENCY_NUM 4 234*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_OSB_FULL_CYCLES 5 235*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_DMA_READ_LATENCY 8 236*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_DMA_READ_LATENCY_NUM 9 237*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_PSB_FULL_CYCLES 10 238*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ICB_FULL_CYCLES 16 239*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ECB_FULL_CYCLES 24 240*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ATU_CSR_CFG_WRITES 32 241*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ATU_CSR_CFG_READS 33 242*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ATU_CSR_MEM_WRITES 34 243*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ATU_CSR_MEM_READS 35 244*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_IMU_CSR_CFG_WRITES 36 245*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_IMU_CSR_CFG_READS 37 246*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_IMU_CSR_MEM_WRITES 38 247*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_IMU_CSR_MEM_READS 39 248*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_NPU_CSR_CFG_WRITES 40 249*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_NPU_CSR_CFG_READS 41 250*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_NPU_CSR_MEM_WRITES 42 251*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_NPU_CSR_MEM_READS 43 252*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_OTHER_CSR_CFG_WRITES 44 253*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_OTHER_CSR_CFG_READS 45 254*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_OTHER_CSR_MEM64_WRITES 46 255*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_OTHER_CSR_MEM64_READS 47 256*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_OTHER_CSR_MEM32_WRITES 48 257*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_OTHER_CSR_MEM32_READS 49 258*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_IO_SPACE_WRITES 50 259*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_IO_SPACE_READS 51 260*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_TOTAL_MSI 52 261*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_ATU_MSI 53 262*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_IMU_MSI 54 263*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_NPU_MSI 55 264*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_RETIRED_TAGS_CTO 56 265*4df55fdeSJanie Lu #define RFIOS_NPU01_EVT_NO_POSTED_TAGS_CYCYLES 57 266*4df55fdeSJanie Lu 267*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_NONE "event_none" 268*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_CLK "clock_cyc" 269*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU0_DMA_WR_REC "peu0_dma_wr_received" 270*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU0_PIO_RD_REC "peu0_pio_rd_received" 271*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU0_DMA_RD_SENT "peu0_dma_rd_sent" 272*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU0_TLP_REC "peu0_tlp_recieved" 273*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU0_TRP_FULL_CYCLES "peu0_trp_full_cyc" 274*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU0_TCH_FULL_CYCLES "peu0_tch_full_cyc" 275*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU0_TCD_FULL_CYCLES "peu0_tcd_full_cyc" 276*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_NON_POSTED_PIOS_LATENCY \ 277*4df55fdeSJanie Lu "non_posted_pios_latency" 278*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_NON_POSTED_PIOS_NUM "non_posted_pios_num" 279*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEX_CFG_WRITE "pex_config_wr" 280*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEX_CFG_READ "pex_config_rd" 281*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEX_MEM_WRITE "pex_mem_wr" 282*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEX_MEM_READ "pex_mem_rd" 283*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU1_DMA_WR_REC "peu1_dma_wr_received" 284*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU1_PIO_RD_REC "peu1_pio_rd_received" 285*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU1_DMA_RD_SENT "peu1_dma_rd_sent" 286*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU1_TLP_REC "peu1_tlp_recieved" 287*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU1_TRP_FULL_CYCLES "peu1_trp_full_cyc" 288*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU1_TCH_FULL_CYCLES "peu1_tch_full_cyc" 289*4df55fdeSJanie Lu #define RFIOS_PEX01_S_EVT_PEU1_TCD_FULL_CYCLES "peu1_tcd_full_cyc" 290*4df55fdeSJanie Lu 291*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_NONE 0x0 292*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_CLK 0x1 293*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU0_DMA_WR_REC 0x2 294*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU0_PIO_RD_REC 0x3 295*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU0_DMA_RD_SENT 0x4 296*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU0_TLP_REC 0x5 297*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU0_TRP_FULL_CYCLES 0x6 298*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU0_TCH_FULL_CYCLES 0x7 299*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU0_TCD_FULL_CYCLES 0x8 300*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_NON_POSTED_PIOS_LATENCY 0x9 301*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_NON_POSTED_PIOS_NUM 0xa 302*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEX_CFG_WRITE 0xb 303*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEX_CFG_READ 0xc 304*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEX_MEM_WRITE 0xd 305*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEX_MEM_READ 0xe 306*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU1_DMA_WR_REC 0x20 307*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU1_PIO_RD_REC 0x30 308*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU1_DMA_RD_SENT 0x40 309*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU1_TLP_REC 0x50 310*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU1_TRP_FULL_CYCLES 0x60 311*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU1_TCH_FULL_CYCLES 0x70 312*4df55fdeSJanie Lu #define RFIOS_PEX01_EVT_PEU1_TCD_FULL_CYCLES 0x80 313*4df55fdeSJanie Lu 314*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_NONE "event_none" 315*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_CLK "clock_cyc" 316*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_INT_CFG_WR_RECD "int_config_wr_recd" 317*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_INT_CFG_RD_RECD "int_config_rd_recd" 318*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_INT_MEM_WR_RECD "int_mem_wr_recd" 319*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_INT_MEM_RD_RECD "int_mem_rd_recd" 320*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_EXT_CFG_WR_RECD "ext_config_wr_recd" 321*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_EXT_CFG_RD_RECD "ext_config_rd_recd" 322*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_EXT_MEM_WR_RECD "ext_mem_wr_recd" 323*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_EXT_MEM_RD_RECD "ext_mem_rd_recd" 324*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_ALL "mem_rd_recd_all" 325*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_1_15DW \ 326*4df55fdeSJanie Lu "mem_rd_recd_1_15dw" 327*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_16_31DW \ 328*4df55fdeSJanie Lu "mem_rd_recd_16_31dw" 329*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_32_63DW \ 330*4df55fdeSJanie Lu "mem_rd_recd_32_63dw" 331*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_64_127DW \ 332*4df55fdeSJanie Lu "mem_rd_recd_64_127dw" 333*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_128_255DW \ 334*4df55fdeSJanie Lu "mem_rd_recd_128_255dw" 335*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_256_511DW \ 336*4df55fdeSJanie Lu "mem_rd_recd_256_511dw" 337*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_512_1024DW \ 338*4df55fdeSJanie Lu "mem_rd_recd_512_1024dw" 339*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_ALL "mem_wr_recd_all" 340*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_1_15DW \ 341*4df55fdeSJanie Lu "mem_wr_recd_1_15dw" 342*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_16_31DW \ 343*4df55fdeSJanie Lu "mem_wr_recd_16_31dw" 344*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_32_63DW \ 345*4df55fdeSJanie Lu "mem_wr_recd_32_63dw" 346*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_64_127DW \ 347*4df55fdeSJanie Lu "mem_wr_recd_64_127dw" 348*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_128_255DW \ 349*4df55fdeSJanie Lu "mem_wr_recd_128_255dw" 350*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_256_511DW \ 351*4df55fdeSJanie Lu "mem_wr_recd_256_511dw" 352*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_512_1024DW \ 353*4df55fdeSJanie Lu "mem_wr_recd_512_1024dw" 354*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_POSTED_HDR_NA_CYC \ 355*4df55fdeSJanie Lu "xmit_posted_hdr_na_cyc" 356*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_POSTED_DATA_NA_CYC \ 357*4df55fdeSJanie Lu "xmit_posted_data_na_cyc" 358*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_NON_POSTED_HDR_NA_CYC \ 359*4df55fdeSJanie Lu "xmit_non_posted_hdr_na_cyc" 360*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_NON_POSTED_DATA_NA_CYC \ 361*4df55fdeSJanie Lu "xmit_non_posted_data_na_cyc" 362*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_COMPL_HDR_NA_CYC "xmit_compl_hdr_na_cyc" 363*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_COMPL_DATA_NA_CYC \ 364*4df55fdeSJanie Lu "xmit_compl_data_na_cyc" 365*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_NO_XMIT_CRED_CYC "no_xmit_cred_cyc" 366*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_RETRY_BUFF_NA_CYC "retry_buffer_na_cyc" 367*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_FLCTRL_COMP_EXST_CYC \ 368*4df55fdeSJanie Lu "rec_flw_compl_hdr_exhast_cyc" 369*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_FLCTRL_NPOST_EXST_CYC \ 370*4df55fdeSJanie Lu "rec_flw_npost_hdr_exhast_cyc" 371*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_FLCTRL_PST_DAT_EXST \ 372*4df55fdeSJanie Lu "rec_flw_post_data_exhast_cyc" 373*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_FLCTRL_PST_DT_CDT_EXST \ 374*4df55fdeSJanie Lu "rec_flw_post_data_cred_exh_cyc" 375*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_FLCTRL_PST_CDT_EXST \ 376*4df55fdeSJanie Lu "rec_flw_post_data_exh_cyc" 377*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_FLCTRL_CDT_EXST "rec_flw_cred_exh_cyc" 378*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_DLLP_CRC_ERRORS "dllp_crc_errs" 379*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_TLP_CRC_ERRORS "tlp_crc_errs" 380*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_TLP_RECD_WITH_EDB "tlp_recd_with_edb" 381*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_RECD_FC_TIMEOUT_ERROR "recd_fc_to_errs" 382*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REPLAY_NUM_ROLLOVERS "replay_num_ro" 383*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REPLAY_TIMER_TIMEOUTS "replay_timer_to" 384*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REPLAYS_INITIATED "replays_init" 385*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_LTSSM_RECOVERY_CYC "ltssm_rec_cyc" 386*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_ENTRIES_LTSSM_RECOVERY \ 387*4df55fdeSJanie Lu "entries_ltssm_rec" 388*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_L0S_STATE_CYC "rec_l0s_state_cyc" 389*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_REC_L0S_STATE_TRANS "rec_l0s_state_trans" 390*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_L0S_STATE_CYC "xmit_l0s_state_cyc" 391*4df55fdeSJanie Lu #define RFIOS_PEU01_S_EVT_XMIT_L0S_STATE_TRANS "xmit_l0s_state_trans" 392*4df55fdeSJanie Lu 393*4df55fdeSJanie Lu 394*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_NONE 0x0 395*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_CLK 0x1 396*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_INT_CFG_WR_RECD 0x2 397*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_INT_CFG_RD_RECD 0x3 398*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_INT_MEM_WR_RECD 0x4 399*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_INT_MEM_RD_RECD 0x5 400*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_EXT_CFG_WR_RECD 0x6 401*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_EXT_CFG_RD_RECD 0x7 402*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_EXT_MEM_WR_RECD 0x8 403*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_EXT_MEM_RD_RECD 0x9 404*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_ALL 0x10 405*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_1_15DW 0x11 406*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_16_31DW 0x12 407*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_32_63DW 0x13 408*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_64_127DW 0x14 409*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_128_255DW 0x15 410*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_256_511DW 0x16 411*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_512_1024DW 0x17 412*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_ALL 0x18 413*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_1_15DW 0x19 414*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_16_31DW 0x1a 415*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_32_63DW 0x1b 416*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_64_127DW 0x1c 417*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_128_255DW 0x1d 418*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_256_511DW 0x1e 419*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_512_1024DW 0x1f 420*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_POSTED_HDR_NA_CYC 0x20 421*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_POSTED_DATA_NA_CYC 0x21 422*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_NON_POSTED_HDR_NA_CYC 0x22 423*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_NON_POSTED_DATA_NA_CYC 0x23 424*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_COMPL_HDR_NA_CYC 0x24 425*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_COMPL_DATA_NA_CYC 0x25 426*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_NO_XMIT_CRED_CYC 0x26 427*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_RETRY_BUFF_NA_CYC 0x27 428*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_FLCTRL_COMP_EXST_CYC 0x28 429*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_FLCTRL_NPOST_EXST_CYC 0x29 430*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_FLCTRL_PST_DAT_EXST 0x2a 431*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_FLCTRL_PST_DT_CDT_EXST 0x2b 432*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_FLCTRL_PST_CDT_EXST 0x2c 433*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_FLCTRL_CDT_EXST 0x2d 434*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_DLLP_CRC_ERRORS 0x30 435*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_TLP_CRC_ERRORS 0x31 436*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_TLP_RECD_WITH_EDB 0x32 437*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_RECD_FC_TIMEOUT_ERROR 0x33 438*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REPLAY_NUM_ROLLOVERS 0x34 439*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REPLAY_TIMER_TIMEOUTS 0x35 440*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REPLAYS_INITIATED 0x36 441*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_LTSSM_RECOVERY_CYC 0x37 442*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_ENTRIES_LTSSM_RECOVERY 0x38 443*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_L0S_STATE_CYC 0x40 444*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_REC_L0S_STATE_TRANS 0x41 445*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_L0S_STATE_CYC 0x42 446*4df55fdeSJanie Lu #define RFIOS_PEU01_EVT_XMIT_L0S_STATE_TRANS 0x43 447*4df55fdeSJanie Lu 448*4df55fdeSJanie Lu extern int rfiospc_get_perfreg(cntr_handle_t handle, int regid, uint64_t *data); 449*4df55fdeSJanie Lu extern int rfiospc_set_perfreg(cntr_handle_t handle, int regid, uint64_t data); 450*4df55fdeSJanie Lu 451*4df55fdeSJanie Lu extern int rfios_access_hv(iospc_t *iospc_p, void *arg, int op, int regid, 452*4df55fdeSJanie Lu uint64_t *data); 453*4df55fdeSJanie Lu extern int rfios_access_init(iospc_t *iospc_p, iospc_ksinfo_t *ksinfo_p); 454*4df55fdeSJanie Lu extern int rfios_access_fini(iospc_t *iospc_p, iospc_ksinfo_t *ksinfo_p); 455*4df55fdeSJanie Lu 456*4df55fdeSJanie Lu #ifdef __cplusplus 457*4df55fdeSJanie Lu } 458*4df55fdeSJanie Lu #endif 459*4df55fdeSJanie Lu 460*4df55fdeSJanie Lu #endif /* _RFIOSPC_TABLES_H */ 461