1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/systm.h> 28 #include <sys/archsystm.h> 29 #include <sys/t_lock.h> 30 #include <sys/uadmin.h> 31 #include <sys/panic.h> 32 #include <sys/reboot.h> 33 #include <sys/autoconf.h> 34 #include <sys/machsystm.h> 35 #include <sys/promif.h> 36 #include <sys/membar.h> 37 #include <vm/hat_sfmmu.h> 38 #include <sys/cpu_module.h> 39 #include <sys/cpu_sgnblk_defs.h> 40 #include <sys/intreg.h> 41 #include <sys/consdev.h> 42 #include <sys/kdi_impl.h> 43 #include <sys/traptrace.h> 44 #include <sys/hypervisor_api.h> 45 #include <sys/vmsystm.h> 46 #include <sys/dtrace.h> 47 #include <sys/xc_impl.h> 48 #include <sys/callb.h> 49 #include <sys/mdesc.h> 50 #include <sys/mach_descrip.h> 51 #include <sys/wdt.h> 52 #include <sys/soft_state.h> 53 #include <sys/promimpl.h> 54 #include <sys/hsvc.h> 55 #include <sys/ldoms.h> 56 #include <sys/kldc.h> 57 #include <sys/clock_impl.h> 58 #include <sys/dumphdr.h> 59 60 /* 61 * hvdump_buf_va is a pointer to the currently-configured hvdump_buf. 62 * A value of NULL indicates that this area is not configured. 63 * hvdump_buf_sz is tunable but will be clamped to HVDUMP_SIZE_MAX. 64 */ 65 66 caddr_t hvdump_buf_va; 67 uint64_t hvdump_buf_sz = HVDUMP_SIZE_DEFAULT; 68 static uint64_t hvdump_buf_pa; 69 70 u_longlong_t panic_tick; 71 72 extern u_longlong_t gettick(); 73 static void reboot_machine(char *); 74 static void update_hvdump_buffer(void); 75 76 /* 77 * For xt_sync synchronization. 78 */ 79 extern uint64_t xc_tick_limit; 80 extern uint64_t xc_tick_jump_limit; 81 extern uint64_t xc_sync_tick_limit; 82 83 /* 84 * We keep our own copies, used for cache flushing, because we can be called 85 * before cpu_fiximpl(). 86 */ 87 static int kdi_dcache_size; 88 static int kdi_dcache_linesize; 89 static int kdi_icache_size; 90 static int kdi_icache_linesize; 91 92 /* 93 * Assembly support for generic modules in sun4v/ml/mach_xc.s 94 */ 95 extern void init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2); 96 extern void kdi_flush_idcache(int, int, int, int); 97 extern uint64_t get_cpuaddr(uint64_t, uint64_t); 98 99 100 #define BOOT_CMD_MAX_LEN 256 101 #define BOOT_CMD_BASE "boot " 102 103 /* 104 * In an LDoms system we do not save the user's boot args in NVRAM 105 * as is done on legacy systems. Instead, we format and send a 106 * 'reboot-command' variable to the variable service. The contents 107 * of the variable are retrieved by OBP and used verbatim for 108 * the next boot. 109 */ 110 static void 111 store_boot_cmd(char *args, boolean_t add_boot_str) 112 { 113 static char cmd_buf[BOOT_CMD_MAX_LEN]; 114 size_t len = 1; 115 pnode_t node; 116 size_t base_len = 0; 117 size_t args_len; 118 size_t args_max; 119 120 if (add_boot_str) { 121 (void) strcpy(cmd_buf, BOOT_CMD_BASE); 122 123 base_len = strlen(BOOT_CMD_BASE); 124 len = base_len + 1; 125 } 126 127 if (args != NULL) { 128 args_len = strlen(args); 129 args_max = BOOT_CMD_MAX_LEN - len; 130 131 if (args_len > args_max) { 132 cmn_err(CE_WARN, "Reboot command too long (%ld), " 133 "truncating command arguments", len + args_len); 134 135 args_len = args_max; 136 } 137 138 len += args_len; 139 (void) strncpy(&cmd_buf[base_len], args, args_len); 140 } 141 142 node = prom_optionsnode(); 143 if ((node == OBP_NONODE) || (node == OBP_BADNODE) || 144 prom_setprop(node, "reboot-command", cmd_buf, len) == -1) 145 cmn_err(CE_WARN, "Unable to store boot command for " 146 "use on reboot"); 147 } 148 149 150 /* 151 * Machine dependent code to reboot. 152 * 153 * "bootstr", when non-null, points to a string to be used as the 154 * argument string when rebooting. 155 * 156 * "invoke_cb" is a boolean. It is set to true when mdboot() can safely 157 * invoke CB_CL_MDBOOT callbacks before shutting the system down, i.e. when 158 * we are in a normal shutdown sequence (interrupts are not blocked, the 159 * system is not panic'ing or being suspended). 160 */ 161 /*ARGSUSED*/ 162 void 163 mdboot(int cmd, int fcn, char *bootstr, boolean_t invoke_cb) 164 { 165 extern void pm_cfb_check_and_powerup(void); 166 167 /* 168 * XXX - rconsvp is set to NULL to ensure that output messages 169 * are sent to the underlying "hardware" device using the 170 * monitor's printf routine since we are in the process of 171 * either rebooting or halting the machine. 172 */ 173 rconsvp = NULL; 174 175 switch (fcn) { 176 case AD_HALT: 177 /* 178 * LDoms: By storing a no-op command 179 * in the 'reboot-command' variable we cause OBP 180 * to ignore the setting of 'auto-boot?' after 181 * it completes the reset. This causes the system 182 * to stop at the ok prompt. 183 */ 184 if (domaining_enabled() && invoke_cb) 185 store_boot_cmd("noop", B_FALSE); 186 break; 187 188 case AD_POWEROFF: 189 break; 190 191 default: 192 if (bootstr == NULL) { 193 switch (fcn) { 194 195 case AD_BOOT: 196 bootstr = ""; 197 break; 198 199 case AD_IBOOT: 200 bootstr = "-a"; 201 break; 202 203 case AD_SBOOT: 204 bootstr = "-s"; 205 break; 206 207 case AD_SIBOOT: 208 bootstr = "-sa"; 209 break; 210 default: 211 cmn_err(CE_WARN, 212 "mdboot: invalid function %d", fcn); 213 bootstr = ""; 214 break; 215 } 216 } 217 218 /* 219 * If LDoms is running, we must save the boot string 220 * before we enter restricted mode. This is possible 221 * only if we are not being called from panic. 222 */ 223 if (domaining_enabled() && invoke_cb) 224 store_boot_cmd(bootstr, B_TRUE); 225 } 226 227 /* 228 * At a high interrupt level we can't: 229 * 1) bring up the console 230 * or 231 * 2) wait for pending interrupts prior to redistribution 232 * to the current CPU 233 * 234 * so we do them now. 235 */ 236 pm_cfb_check_and_powerup(); 237 238 /* make sure there are no more changes to the device tree */ 239 devtree_freeze(); 240 241 if (invoke_cb) 242 (void) callb_execute_class(CB_CL_MDBOOT, NULL); 243 244 /* 245 * Clear any unresolved UEs from memory. 246 */ 247 page_retire_mdboot(); 248 249 /* 250 * stop other cpus which also raise our priority. since there is only 251 * one active cpu after this, and our priority will be too high 252 * for us to be preempted, we're essentially single threaded 253 * from here on out. 254 */ 255 stop_other_cpus(); 256 257 /* 258 * try and reset leaf devices. reset_leaves() should only 259 * be called when there are no other threads that could be 260 * accessing devices 261 */ 262 reset_leaves(); 263 264 watchdog_clear(); 265 266 if (fcn == AD_HALT) { 267 mach_set_soft_state(SIS_TRANSITION, 268 &SOLARIS_SOFT_STATE_HALT_MSG); 269 halt((char *)NULL); 270 } else if (fcn == AD_POWEROFF) { 271 mach_set_soft_state(SIS_TRANSITION, 272 &SOLARIS_SOFT_STATE_POWER_MSG); 273 power_down(NULL); 274 } else { 275 mach_set_soft_state(SIS_TRANSITION, 276 &SOLARIS_SOFT_STATE_REBOOT_MSG); 277 reboot_machine(bootstr); 278 } 279 /* MAYBE REACHED */ 280 } 281 282 /* mdpreboot - may be called prior to mdboot while root fs still mounted */ 283 /*ARGSUSED*/ 284 void 285 mdpreboot(int cmd, int fcn, char *bootstr) 286 { 287 } 288 289 /* 290 * Halt the machine and then reboot with the device 291 * and arguments specified in bootstr. 292 */ 293 static void 294 reboot_machine(char *bootstr) 295 { 296 flush_windows(); 297 stop_other_cpus(); /* send stop signal to other CPUs */ 298 prom_printf("rebooting...\n"); 299 /* 300 * For platforms that use CPU signatures, we 301 * need to set the signature block to OS and 302 * the state to exiting for all the processors. 303 */ 304 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_REBOOT, -1); 305 prom_reboot(bootstr); 306 /*NOTREACHED*/ 307 } 308 309 /* 310 * We use the x-trap mechanism and idle_stop_xcall() to stop the other CPUs. 311 * Once in panic_idle() they raise spl, record their location, and spin. 312 */ 313 static void 314 panic_idle(void) 315 { 316 (void) spl7(); 317 318 debug_flush_windows(); 319 (void) setjmp(&curthread->t_pcb); 320 321 CPU->cpu_m.in_prom = 1; 322 membar_stld(); 323 324 dumpsys_helper(); 325 326 for (;;) 327 ; 328 } 329 330 /* 331 * Force the other CPUs to trap into panic_idle(), and then remove them 332 * from the cpu_ready_set so they will no longer receive cross-calls. 333 */ 334 /*ARGSUSED*/ 335 void 336 panic_stopcpus(cpu_t *cp, kthread_t *t, int spl) 337 { 338 cpuset_t cps; 339 int i; 340 341 (void) splzs(); 342 CPUSET_ALL_BUT(cps, cp->cpu_id); 343 xt_some(cps, (xcfunc_t *)idle_stop_xcall, (uint64_t)&panic_idle, NULL); 344 345 for (i = 0; i < NCPU; i++) { 346 if (i != cp->cpu_id && CPU_XCALL_READY(i)) { 347 int ntries = 0x10000; 348 349 while (!cpu[i]->cpu_m.in_prom && ntries) { 350 DELAY(50); 351 ntries--; 352 } 353 354 if (!cpu[i]->cpu_m.in_prom) 355 printf("panic: failed to stop cpu%d\n", i); 356 357 cpu[i]->cpu_flags &= ~CPU_READY; 358 cpu[i]->cpu_flags |= CPU_QUIESCED; 359 CPUSET_DEL(cpu_ready_set, cpu[i]->cpu_id); 360 } 361 } 362 } 363 364 /* 365 * Platform callback following each entry to panicsys(). If we've panicked at 366 * level 14, we examine t_panic_trap to see if a fatal trap occurred. If so, 367 * we disable further %tick_cmpr interrupts. If not, an explicit call to panic 368 * was made and so we re-enqueue an interrupt request structure to allow 369 * further level 14 interrupts to be processed once we lower PIL. This allows 370 * us to handle panics from the deadman() CY_HIGH_LEVEL cyclic. 371 */ 372 void 373 panic_enter_hw(int spl) 374 { 375 if (!panic_tick) { 376 panic_tick = gettick(); 377 if (mach_htraptrace_enable) { 378 uint64_t prev_freeze; 379 380 /* there are no possible error codes for this hcall */ 381 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 382 &prev_freeze); 383 } 384 #ifdef TRAPTRACE 385 TRAPTRACE_FREEZE; 386 #endif 387 } 388 389 mach_set_soft_state(SIS_TRANSITION, &SOLARIS_SOFT_STATE_PANIC_MSG); 390 391 if (spl == ipltospl(PIL_14)) { 392 uint_t opstate = disable_vec_intr(); 393 394 if (curthread->t_panic_trap != NULL) { 395 tickcmpr_disable(); 396 intr_dequeue_req(PIL_14, cbe_level14_inum); 397 } else { 398 if (!tickcmpr_disabled()) 399 intr_enqueue_req(PIL_14, cbe_level14_inum); 400 /* 401 * Clear SOFTINT<14>, SOFTINT<0> (TICK_INT) 402 * and SOFTINT<16> (STICK_INT) to indicate 403 * that the current level 14 has been serviced. 404 */ 405 wr_clr_softint((1 << PIL_14) | 406 TICK_INT_MASK | STICK_INT_MASK); 407 } 408 409 enable_vec_intr(opstate); 410 } 411 } 412 413 /* 414 * Miscellaneous hardware-specific code to execute after panicstr is set 415 * by the panic code: we also print and record PTL1 panic information here. 416 */ 417 /*ARGSUSED*/ 418 void 419 panic_quiesce_hw(panic_data_t *pdp) 420 { 421 extern uint_t getpstate(void); 422 extern void setpstate(uint_t); 423 424 /* 425 * Turn off TRAPTRACE and save the current %tick value in panic_tick. 426 */ 427 if (!panic_tick) { 428 panic_tick = gettick(); 429 if (mach_htraptrace_enable) { 430 uint64_t prev_freeze; 431 432 /* there are no possible error codes for this hcall */ 433 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 434 &prev_freeze); 435 } 436 #ifdef TRAPTRACE 437 TRAPTRACE_FREEZE; 438 #endif 439 } 440 /* 441 * For Platforms that use CPU signatures, we 442 * need to set the signature block to OS, the state to 443 * exiting, and the substate to panic for all the processors. 444 */ 445 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_PANIC, -1); 446 447 update_hvdump_buffer(); 448 449 /* 450 * Disable further ECC errors from the bus nexus. 451 */ 452 (void) bus_func_invoke(BF_TYPE_ERRDIS); 453 454 /* 455 * Redirect all interrupts to the current CPU. 456 */ 457 intr_redist_all_cpus_shutdown(); 458 459 /* 460 * This call exists solely to support dumps to network 461 * devices after sync from OBP. 462 * 463 * If we came here via the sync callback, then on some 464 * platforms, interrupts may have arrived while we were 465 * stopped in OBP. OBP will arrange for those interrupts to 466 * be redelivered if you say "go", but not if you invoke a 467 * client callback like 'sync'. For some dump devices 468 * (network swap devices), we need interrupts to be 469 * delivered in order to dump, so we have to call the bus 470 * nexus driver to reset the interrupt state machines. 471 */ 472 (void) bus_func_invoke(BF_TYPE_RESINTR); 473 474 setpstate(getpstate() | PSTATE_IE); 475 } 476 477 /* 478 * Platforms that use CPU signatures need to set the signature block to OS and 479 * the state to exiting for all CPUs. PANIC_CONT indicates that we're about to 480 * write the crash dump, which tells the SSP/SMS to begin a timeout routine to 481 * reboot the machine if the dump never completes. 482 */ 483 /*ARGSUSED*/ 484 void 485 panic_dump_hw(int spl) 486 { 487 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_DUMP, -1); 488 } 489 490 /* 491 * for ptl1_panic 492 */ 493 void 494 ptl1_init_cpu(struct cpu *cpu) 495 { 496 ptl1_state_t *pstate = &cpu->cpu_m.ptl1_state; 497 498 /*CONSTCOND*/ 499 if (sizeof (struct cpu) + PTL1_SSIZE > CPU_ALLOC_SIZE) { 500 panic("ptl1_init_cpu: not enough space left for ptl1_panic " 501 "stack, sizeof (struct cpu) = %lu", 502 (unsigned long)sizeof (struct cpu)); 503 } 504 505 pstate->ptl1_stktop = (uintptr_t)cpu + CPU_ALLOC_SIZE; 506 cpu_pa[cpu->cpu_id] = va_to_pa(cpu); 507 } 508 509 void 510 ptl1_panic_handler(ptl1_state_t *pstate) 511 { 512 static const char *ptl1_reasons[] = { 513 #ifdef PTL1_PANIC_DEBUG 514 "trap for debug purpose", /* PTL1_BAD_DEBUG */ 515 #else 516 "unknown trap", /* PTL1_BAD_DEBUG */ 517 #endif 518 "register window trap", /* PTL1_BAD_WTRAP */ 519 "kernel MMU miss", /* PTL1_BAD_KMISS */ 520 "kernel protection fault", /* PTL1_BAD_KPROT_FAULT */ 521 "ISM MMU miss", /* PTL1_BAD_ISM */ 522 "kernel MMU trap", /* PTL1_BAD_MMUTRAP */ 523 "kernel trap handler state", /* PTL1_BAD_TRAP */ 524 "floating point trap", /* PTL1_BAD_FPTRAP */ 525 #ifdef DEBUG 526 "pointer to intr_vec", /* PTL1_BAD_INTR_VEC */ 527 #else 528 "unknown trap", /* PTL1_BAD_INTR_VEC */ 529 #endif 530 #ifdef TRAPTRACE 531 "TRACE_PTR state", /* PTL1_BAD_TRACE_PTR */ 532 #else 533 "unknown trap", /* PTL1_BAD_TRACE_PTR */ 534 #endif 535 "stack overflow", /* PTL1_BAD_STACK */ 536 "DTrace flags", /* PTL1_BAD_DTRACE_FLAGS */ 537 "attempt to steal locked ctx", /* PTL1_BAD_CTX_STEAL */ 538 "CPU ECC error loop", /* PTL1_BAD_ECC */ 539 "unexpected error from hypervisor call", /* PTL1_BAD_HCALL */ 540 "unexpected global level(%gl)", /* PTL1_BAD_GL */ 541 "Watchdog Reset", /* PTL1_BAD_WATCHDOG */ 542 "unexpected RED mode trap", /* PTL1_BAD_RED */ 543 "return value EINVAL from hcall: "\ 544 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_EINVAL */ 545 "return value ENOMAP from hcall: "\ 546 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_ENOMAP */ 547 "error raising a TSB exception", /* PTL1_BAD_RAISE_TSBEXCP */ 548 "missing shared TSB" /* PTL1_NO_SCDTSB8K */ 549 }; 550 551 uint_t reason = pstate->ptl1_regs.ptl1_gregs[0].ptl1_g1; 552 uint_t tl = pstate->ptl1_regs.ptl1_trap_regs[0].ptl1_tl; 553 struct panic_trap_info ti = { 0 }; 554 555 /* 556 * Use trap_info for a place holder to call panic_savetrap() and 557 * panic_showtrap() to save and print out ptl1_panic information. 558 */ 559 if (curthread->t_panic_trap == NULL) 560 curthread->t_panic_trap = &ti; 561 562 if (reason < sizeof (ptl1_reasons) / sizeof (ptl1_reasons[0])) 563 panic("bad %s at TL %u", ptl1_reasons[reason], tl); 564 else 565 panic("ptl1_panic reason 0x%x at TL %u", reason, tl); 566 } 567 568 void 569 clear_watchdog_on_exit(void) 570 { 571 if (watchdog_enabled && watchdog_activated) { 572 prom_printf("Debugging requested; hardware watchdog " 573 "suspended.\n"); 574 (void) watchdog_suspend(); 575 } 576 } 577 578 /* 579 * Restore the watchdog timer when returning from a debugger 580 * after a panic or L1-A and resume watchdog pat. 581 */ 582 void 583 restore_watchdog_on_entry() 584 { 585 watchdog_resume(); 586 } 587 588 int 589 kdi_watchdog_disable(void) 590 { 591 watchdog_suspend(); 592 593 return (0); 594 } 595 596 void 597 kdi_watchdog_restore(void) 598 { 599 watchdog_resume(); 600 } 601 602 void 603 mach_dump_buffer_init(void) 604 { 605 uint64_t ret, minsize = 0; 606 607 if (hvdump_buf_sz > HVDUMP_SIZE_MAX) 608 hvdump_buf_sz = HVDUMP_SIZE_MAX; 609 610 hvdump_buf_va = contig_mem_alloc_align(hvdump_buf_sz, PAGESIZE); 611 if (hvdump_buf_va == NULL) 612 return; 613 614 hvdump_buf_pa = va_to_pa(hvdump_buf_va); 615 616 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 617 &minsize); 618 619 if (ret != H_EOK) { 620 contig_mem_free(hvdump_buf_va, hvdump_buf_sz); 621 hvdump_buf_va = NULL; 622 cmn_err(CE_NOTE, "!Error in setting up hvstate" 623 "dump buffer. Error = 0x%lx, size = 0x%lx," 624 "buf_pa = 0x%lx", ret, hvdump_buf_sz, 625 hvdump_buf_pa); 626 627 if (ret == H_EINVAL) { 628 cmn_err(CE_NOTE, "!Buffer size too small." 629 "Available buffer size = 0x%lx," 630 "Minimum buffer size required = 0x%lx", 631 hvdump_buf_sz, minsize); 632 } 633 } 634 } 635 636 637 static void 638 update_hvdump_buffer(void) 639 { 640 uint64_t ret, dummy_val; 641 642 if (hvdump_buf_va == NULL) 643 return; 644 645 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 646 &dummy_val); 647 if (ret != H_EOK) { 648 cmn_err(CE_NOTE, "!Cannot update hvstate dump" 649 "buffer. Error = 0x%lx", ret); 650 } 651 } 652 653 654 static int 655 getintprop(pnode_t node, char *name, int deflt) 656 { 657 int value; 658 659 switch (prom_getproplen(node, name)) { 660 case 0: 661 value = 1; /* boolean properties */ 662 break; 663 664 case sizeof (int): 665 (void) prom_getprop(node, name, (caddr_t)&value); 666 break; 667 668 default: 669 value = deflt; 670 break; 671 } 672 673 return (value); 674 } 675 676 /* 677 * Called by setcpudelay 678 */ 679 void 680 cpu_init_tick_freq(void) 681 { 682 md_t *mdp; 683 mde_cookie_t rootnode; 684 int listsz; 685 mde_cookie_t *listp = NULL; 686 int num_nodes; 687 uint64_t stick_prop; 688 689 if (broken_md_flag) { 690 sys_tick_freq = cpunodes[CPU->cpu_id].clock_freq; 691 return; 692 } 693 694 if ((mdp = md_get_handle()) == NULL) 695 panic("stick_frequency property not found in MD"); 696 697 rootnode = md_root_node(mdp); 698 ASSERT(rootnode != MDE_INVAL_ELEM_COOKIE); 699 700 num_nodes = md_node_count(mdp); 701 702 ASSERT(num_nodes > 0); 703 listsz = num_nodes * sizeof (mde_cookie_t); 704 listp = (mde_cookie_t *)prom_alloc((caddr_t)0, listsz, 0); 705 706 if (listp == NULL) 707 panic("cannot allocate list for MD properties"); 708 709 num_nodes = md_scan_dag(mdp, rootnode, md_find_name(mdp, "platform"), 710 md_find_name(mdp, "fwd"), listp); 711 712 ASSERT(num_nodes == 1); 713 714 if (md_get_prop_val(mdp, *listp, "stick-frequency", &stick_prop) != 0) 715 panic("stick_frequency property not found in MD"); 716 717 sys_tick_freq = stick_prop; 718 719 prom_free((caddr_t)listp, listsz); 720 (void) md_fini_handle(mdp); 721 } 722 723 int shipit(int n, uint64_t cpu_list_ra); 724 725 #ifdef DEBUG 726 #define SEND_MONDO_STATS 1 727 #endif 728 729 #ifdef SEND_MONDO_STATS 730 uint32_t x_one_stimes[64]; 731 uint32_t x_one_ltimes[16]; 732 uint32_t x_set_stimes[64]; 733 uint32_t x_set_ltimes[16]; 734 uint32_t x_set_cpus[NCPU]; 735 #endif 736 737 void 738 send_one_mondo(int cpuid) 739 { 740 int retries, stat; 741 uint64_t starttick, endtick, tick, lasttick; 742 struct machcpu *mcpup = &(CPU->cpu_m); 743 744 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 745 starttick = lasttick = gettick(); 746 mcpup->cpu_list[0] = (uint16_t)cpuid; 747 stat = shipit(1, mcpup->cpu_list_ra); 748 endtick = starttick + xc_tick_limit; 749 retries = 0; 750 while (stat != H_EOK) { 751 if (stat != H_EWOULDBLOCK) { 752 if (panic_quiesce) 753 return; 754 if (stat == H_ECPUERROR) 755 cmn_err(CE_PANIC, "send_one_mondo: " 756 "cpuid: 0x%x has been marked in " 757 "error", cpuid); 758 else 759 cmn_err(CE_PANIC, "send_one_mondo: " 760 "unexpected hypervisor error 0x%x " 761 "while sending a mondo to cpuid: " 762 "0x%x", stat, cpuid); 763 } 764 tick = gettick(); 765 /* 766 * If there is a big jump between the current tick 767 * count and lasttick, we have probably hit a break 768 * point. Adjust endtick accordingly to avoid panic. 769 */ 770 if (tick > (lasttick + xc_tick_jump_limit)) 771 endtick += (tick - lasttick); 772 lasttick = tick; 773 if (tick > endtick) { 774 if (panic_quiesce) 775 return; 776 cmn_err(CE_PANIC, "send mondo timeout " 777 "(target 0x%x) [retries: 0x%x hvstat: 0x%x]", 778 cpuid, retries, stat); 779 } 780 drv_usecwait(1); 781 stat = shipit(1, mcpup->cpu_list_ra); 782 retries++; 783 } 784 #ifdef SEND_MONDO_STATS 785 { 786 uint64_t n = gettick() - starttick; 787 if (n < 8192) 788 x_one_stimes[n >> 7]++; 789 else if (n < 15*8192) 790 x_one_ltimes[n >> 13]++; 791 else 792 x_one_ltimes[0xf]++; 793 } 794 #endif 795 } 796 797 void 798 send_mondo_set(cpuset_t set) 799 { 800 uint64_t starttick, endtick, tick, lasttick; 801 uint_t largestid, smallestid; 802 int i, j; 803 int ncpuids = 0; 804 int shipped = 0; 805 int retries = 0; 806 struct machcpu *mcpup = &(CPU->cpu_m); 807 808 ASSERT(!CPUSET_ISNULL(set)); 809 CPUSET_BOUNDS(set, smallestid, largestid); 810 if (smallestid == CPUSET_NOTINSET) { 811 return; 812 } 813 814 starttick = lasttick = gettick(); 815 endtick = starttick + xc_tick_limit; 816 817 /* 818 * Assemble CPU list for HV argument. We already know 819 * smallestid and largestid are members of set. 820 */ 821 mcpup->cpu_list[ncpuids++] = (uint16_t)smallestid; 822 if (largestid != smallestid) { 823 for (i = smallestid+1; i <= largestid-1; i++) { 824 if (CPU_IN_SET(set, i)) { 825 mcpup->cpu_list[ncpuids++] = (uint16_t)i; 826 } 827 } 828 mcpup->cpu_list[ncpuids++] = (uint16_t)largestid; 829 } 830 831 do { 832 int stat; 833 834 stat = shipit(ncpuids, mcpup->cpu_list_ra); 835 if (stat == H_EOK) { 836 shipped += ncpuids; 837 break; 838 } 839 840 /* 841 * Either not all CPU mondos were sent, or an 842 * error occurred. CPUs that were sent mondos 843 * have their CPU IDs overwritten in cpu_list. 844 * Reset cpu_list so that it only holds those 845 * CPU IDs that still need to be sent. 846 */ 847 for (i = 0, j = 0; i < ncpuids; i++) { 848 if (mcpup->cpu_list[i] == HV_SEND_MONDO_ENTRYDONE) { 849 shipped++; 850 } else { 851 mcpup->cpu_list[j++] = mcpup->cpu_list[i]; 852 } 853 } 854 ncpuids = j; 855 856 /* 857 * Now handle possible errors returned 858 * from hypervisor. 859 */ 860 if (stat == H_ECPUERROR) { 861 int errorcpus; 862 863 if (!panic_quiesce) 864 cmn_err(CE_CONT, "send_mondo_set: cpuid(s) "); 865 866 /* 867 * Remove any CPUs in the error state from 868 * cpu_list. At this point cpu_list only 869 * contains the CPU IDs for mondos not 870 * succesfully sent. 871 */ 872 for (i = 0, errorcpus = 0; i < ncpuids; i++) { 873 uint64_t state = CPU_STATE_INVALID; 874 uint16_t id = mcpup->cpu_list[i]; 875 876 (void) hv_cpu_state(id, &state); 877 if (state == CPU_STATE_ERROR) { 878 if (!panic_quiesce) 879 cmn_err(CE_CONT, "0x%x ", id); 880 errorcpus++; 881 } else if (errorcpus > 0) { 882 mcpup->cpu_list[i - errorcpus] = 883 mcpup->cpu_list[i]; 884 } 885 } 886 ncpuids -= errorcpus; 887 888 if (!panic_quiesce) { 889 if (errorcpus == 0) { 890 cmn_err(CE_CONT, "<none> have been " 891 "marked in error\n"); 892 cmn_err(CE_PANIC, "send_mondo_set: " 893 "hypervisor returned " 894 "H_ECPUERROR but no CPU in " 895 "cpu_list in error state"); 896 } else { 897 cmn_err(CE_CONT, "have been marked in " 898 "error\n"); 899 cmn_err(CE_PANIC, "send_mondo_set: " 900 "CPU(s) in error state"); 901 } 902 } 903 } else if (stat != H_EWOULDBLOCK) { 904 if (panic_quiesce) 905 return; 906 /* 907 * For all other errors, panic. 908 */ 909 cmn_err(CE_CONT, "send_mondo_set: unexpected " 910 "hypervisor error 0x%x while sending a " 911 "mondo to cpuid(s):", stat); 912 for (i = 0; i < ncpuids; i++) { 913 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 914 } 915 cmn_err(CE_CONT, "\n"); 916 cmn_err(CE_PANIC, "send_mondo_set: unexpected " 917 "hypervisor error"); 918 } 919 920 tick = gettick(); 921 /* 922 * If there is a big jump between the current tick 923 * count and lasttick, we have probably hit a break 924 * point. Adjust endtick accordingly to avoid panic. 925 */ 926 if (tick > (lasttick + xc_tick_jump_limit)) 927 endtick += (tick - lasttick); 928 lasttick = tick; 929 if (tick > endtick) { 930 if (panic_quiesce) 931 return; 932 cmn_err(CE_CONT, "send mondo timeout " 933 "[retries: 0x%x] cpuids: ", retries); 934 for (i = 0; i < ncpuids; i++) 935 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 936 cmn_err(CE_CONT, "\n"); 937 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 938 } 939 940 while (gettick() < (tick + sys_clock_mhz)) 941 ; 942 retries++; 943 } while (ncpuids > 0); 944 945 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 946 947 #ifdef SEND_MONDO_STATS 948 { 949 uint64_t n = gettick() - starttick; 950 if (n < 8192) 951 x_set_stimes[n >> 7]++; 952 else if (n < 15*8192) 953 x_set_ltimes[n >> 13]++; 954 else 955 x_set_ltimes[0xf]++; 956 } 957 x_set_cpus[shipped]++; 958 #endif 959 } 960 961 void 962 syncfpu(void) 963 { 964 } 965 966 void 967 sticksync_slave(void) 968 {} 969 970 void 971 sticksync_master(void) 972 {} 973 974 void 975 cpu_init_cache_scrub(void) 976 { 977 mach_set_soft_state(SIS_NORMAL, &SOLARIS_SOFT_STATE_RUN_MSG); 978 } 979 980 int 981 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 982 { 983 int ret, watched; 984 985 watched = watch_disable_addr((void *)addr, 4, S_WRITE); 986 ret = dtrace_blksuword32(addr, data, 0); 987 if (watched) 988 watch_enable_addr((void *)addr, 4, S_WRITE); 989 990 return (ret); 991 } 992 993 int 994 dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain) 995 { 996 if (suword32((void *)addr, *data) == -1) 997 return (tryagain ? dtrace_blksuword32_err(addr, data) : -1); 998 dtrace_flush_sec(addr); 999 1000 return (0); 1001 } 1002 1003 /*ARGSUSED*/ 1004 void 1005 cpu_faulted_enter(struct cpu *cp) 1006 { 1007 } 1008 1009 /*ARGSUSED*/ 1010 void 1011 cpu_faulted_exit(struct cpu *cp) 1012 { 1013 } 1014 1015 static int 1016 kdi_cpu_ready_iter(int (*cb)(int, void *), void *arg) 1017 { 1018 int rc, i; 1019 1020 for (rc = 0, i = 0; i < NCPU; i++) { 1021 if (CPU_IN_SET(cpu_ready_set, i)) 1022 rc += cb(i, arg); 1023 } 1024 1025 return (rc); 1026 } 1027 1028 /* 1029 * Sends a cross-call to a specified processor. The caller assumes 1030 * responsibility for repetition of cross-calls, as appropriate (MARSA for 1031 * debugging). 1032 */ 1033 static int 1034 kdi_xc_one(int cpuid, void (*func)(uintptr_t, uintptr_t), uintptr_t arg1, 1035 uintptr_t arg2) 1036 { 1037 int stat; 1038 struct machcpu *mcpup; 1039 uint64_t cpuaddr_reg = 0, cpuaddr_scr = 0; 1040 1041 mcpup = &(((cpu_t *)get_cpuaddr(cpuaddr_reg, cpuaddr_scr))->cpu_m); 1042 1043 /* 1044 * if (idsr_busy()) 1045 * return (KDI_XC_RES_ERR); 1046 */ 1047 1048 init_mondo_nocheck((xcfunc_t *)func, arg1, arg2); 1049 1050 mcpup->cpu_list[0] = (uint16_t)cpuid; 1051 stat = shipit(1, mcpup->cpu_list_ra); 1052 1053 if (stat == 0) 1054 return (KDI_XC_RES_OK); 1055 else 1056 return (KDI_XC_RES_NACK); 1057 } 1058 1059 static void 1060 kdi_tickwait(clock_t nticks) 1061 { 1062 clock_t endtick = gettick() + nticks; 1063 1064 while (gettick() < endtick) 1065 ; 1066 } 1067 1068 static void 1069 kdi_cpu_init(int dcache_size, int dcache_linesize, int icache_size, 1070 int icache_linesize) 1071 { 1072 kdi_dcache_size = dcache_size; 1073 kdi_dcache_linesize = dcache_linesize; 1074 kdi_icache_size = icache_size; 1075 kdi_icache_linesize = icache_linesize; 1076 } 1077 1078 /* used directly by kdi_read/write_phys */ 1079 void 1080 kdi_flush_caches(void) 1081 { 1082 /* Not required on sun4v architecture. */ 1083 } 1084 1085 /*ARGSUSED*/ 1086 int 1087 kdi_get_stick(uint64_t *stickp) 1088 { 1089 return (-1); 1090 } 1091 1092 void 1093 cpu_kdi_init(kdi_t *kdi) 1094 { 1095 kdi->kdi_flush_caches = kdi_flush_caches; 1096 kdi->mkdi_cpu_init = kdi_cpu_init; 1097 kdi->mkdi_cpu_ready_iter = kdi_cpu_ready_iter; 1098 kdi->mkdi_xc_one = kdi_xc_one; 1099 kdi->mkdi_tickwait = kdi_tickwait; 1100 kdi->mkdi_get_stick = kdi_get_stick; 1101 } 1102 1103 uint64_t soft_state_message_ra[SOLARIS_SOFT_STATE_MSG_CNT]; 1104 static uint64_t soft_state_saved_state = (uint64_t)-1; 1105 static int soft_state_initialized = 0; 1106 static uint64_t soft_state_sup_minor; /* Supported minor number */ 1107 static hsvc_info_t soft_state_hsvc = { 1108 HSVC_REV_1, NULL, HSVC_GROUP_SOFT_STATE, 1, 0, NULL }; 1109 1110 1111 static void 1112 sun4v_system_claim(void) 1113 { 1114 lbolt_debug_entry(); 1115 1116 watchdog_suspend(); 1117 kldc_debug_enter(); 1118 /* 1119 * For "mdb -K", set soft state to debugging 1120 */ 1121 if (soft_state_saved_state == -1) { 1122 mach_get_soft_state(&soft_state_saved_state, 1123 &SOLARIS_SOFT_STATE_SAVED_MSG); 1124 } 1125 /* 1126 * check again as the read above may or may not have worked and if 1127 * it didn't then soft state will still be -1 1128 */ 1129 if (soft_state_saved_state != -1) { 1130 mach_set_soft_state(SIS_TRANSITION, 1131 &SOLARIS_SOFT_STATE_DEBUG_MSG); 1132 } 1133 } 1134 1135 static void 1136 sun4v_system_release(void) 1137 { 1138 watchdog_resume(); 1139 /* 1140 * For "mdb -K", set soft_state state back to original state on exit 1141 */ 1142 if (soft_state_saved_state != -1) { 1143 mach_set_soft_state(soft_state_saved_state, 1144 &SOLARIS_SOFT_STATE_SAVED_MSG); 1145 soft_state_saved_state = -1; 1146 } 1147 1148 lbolt_debug_return(); 1149 } 1150 1151 void 1152 plat_kdi_init(kdi_t *kdi) 1153 { 1154 kdi->pkdi_system_claim = sun4v_system_claim; 1155 kdi->pkdi_system_release = sun4v_system_release; 1156 } 1157 1158 /* 1159 * Routine to return memory information associated 1160 * with a physical address and syndrome. 1161 */ 1162 /* ARGSUSED */ 1163 int 1164 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1165 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1166 int *segsp, int *banksp, int *mcidp) 1167 { 1168 return (ENOTSUP); 1169 } 1170 1171 /* 1172 * This routine returns the size of the kernel's FRU name buffer. 1173 */ 1174 size_t 1175 cpu_get_name_bufsize() 1176 { 1177 return (UNUM_NAMLEN); 1178 } 1179 1180 /* 1181 * This routine is a more generic interface to cpu_get_mem_unum(), 1182 * that may be used by other modules (e.g. mm). 1183 */ 1184 /* ARGSUSED */ 1185 int 1186 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1187 char *buf, int buflen, int *lenp) 1188 { 1189 return (ENOTSUP); 1190 } 1191 1192 /* ARGSUSED */ 1193 int 1194 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 1195 { 1196 return (ENOTSUP); 1197 } 1198 1199 /* ARGSUSED */ 1200 int 1201 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 1202 { 1203 return (ENOTSUP); 1204 } 1205 1206 /* 1207 * xt_sync - wait for previous x-traps to finish 1208 */ 1209 void 1210 xt_sync(cpuset_t cpuset) 1211 { 1212 union { 1213 uint8_t volatile byte[NCPU]; 1214 uint64_t volatile xword[NCPU / 8]; 1215 } cpu_sync; 1216 uint64_t starttick, endtick, tick, lasttick, traptrace_id; 1217 uint_t largestid, smallestid; 1218 int i, j; 1219 1220 kpreempt_disable(); 1221 CPUSET_DEL(cpuset, CPU->cpu_id); 1222 CPUSET_AND(cpuset, cpu_ready_set); 1223 1224 CPUSET_BOUNDS(cpuset, smallestid, largestid); 1225 if (smallestid == CPUSET_NOTINSET) 1226 goto out; 1227 1228 /* 1229 * Sun4v uses a queue for receiving mondos. Successful 1230 * transmission of a mondo only indicates that the mondo 1231 * has been written into the queue. 1232 * 1233 * We use an array of bytes to let each cpu to signal back 1234 * to the cross trap sender that the cross trap has been 1235 * executed. Set the byte to 1 before sending the cross trap 1236 * and wait until other cpus reset it to 0. 1237 */ 1238 bzero((void *)&cpu_sync, NCPU); 1239 cpu_sync.byte[smallestid] = 1; 1240 if (largestid != smallestid) { 1241 for (i = (smallestid + 1); i <= (largestid - 1); i++) 1242 if (CPU_IN_SET(cpuset, i)) 1243 cpu_sync.byte[i] = 1; 1244 cpu_sync.byte[largestid] = 1; 1245 } 1246 1247 /* 1248 * To help debug xt_sync panic, each mondo is uniquely identified 1249 * by passing the tick value, traptrace_id as the second mondo 1250 * argument to xt_some which is logged in CPU's mondo queue, 1251 * traptrace buffer and the panic message. 1252 */ 1253 traptrace_id = gettick(); 1254 xt_some(cpuset, (xcfunc_t *)xt_sync_tl1, 1255 (uint64_t)cpu_sync.byte, traptrace_id); 1256 1257 starttick = lasttick = gettick(); 1258 endtick = starttick + xc_sync_tick_limit; 1259 1260 for (i = (smallestid / 8); i <= (largestid / 8); i++) { 1261 while (cpu_sync.xword[i] != 0) { 1262 tick = gettick(); 1263 /* 1264 * If there is a big jump between the current tick 1265 * count and lasttick, we have probably hit a break 1266 * point. Adjust endtick accordingly to avoid panic. 1267 */ 1268 if (tick > (lasttick + xc_tick_jump_limit)) { 1269 endtick += (tick - lasttick); 1270 } 1271 lasttick = tick; 1272 if (tick > endtick) { 1273 if (panic_quiesce) 1274 goto out; 1275 cmn_err(CE_CONT, "Cross trap sync timeout: " 1276 "at cpu_sync.xword[%d]: 0x%lx " 1277 "cpu_sync.byte: 0x%lx " 1278 "starttick: 0x%lx endtick: 0x%lx " 1279 "traptrace_id = 0x%lx\n", 1280 i, cpu_sync.xword[i], 1281 (uint64_t)cpu_sync.byte, 1282 starttick, endtick, traptrace_id); 1283 cmn_err(CE_CONT, "CPUIDs:"); 1284 for (j = (i * 8); j <= largestid; j++) { 1285 if (cpu_sync.byte[j] != 0) 1286 cmn_err(CE_CONT, " 0x%x", j); 1287 } 1288 cmn_err(CE_PANIC, "xt_sync: timeout"); 1289 } 1290 } 1291 } 1292 1293 out: 1294 kpreempt_enable(); 1295 } 1296 1297 #define QFACTOR 200 1298 /* 1299 * Recalculate the values of the cross-call timeout variables based 1300 * on the value of the 'inter-cpu-latency' property of the platform node. 1301 * The property sets the number of nanosec to wait for a cross-call 1302 * to be acknowledged. Other timeout variables are derived from it. 1303 * 1304 * N.B. This implementation is aware of the internals of xc_init() 1305 * and updates many of the same variables. 1306 */ 1307 void 1308 recalc_xc_timeouts(void) 1309 { 1310 typedef union { 1311 uint64_t whole; 1312 struct { 1313 uint_t high; 1314 uint_t low; 1315 } half; 1316 } u_number; 1317 1318 /* See x_call.c for descriptions of these extern variables. */ 1319 extern uint64_t xc_tick_limit_scale; 1320 extern uint64_t xc_mondo_time_limit; 1321 extern uint64_t xc_func_time_limit; 1322 extern uint64_t xc_scale; 1323 extern uint64_t xc_mondo_multiplier; 1324 extern uint_t nsec_shift; 1325 1326 /* Temp versions of the target variables */ 1327 uint64_t tick_limit; 1328 uint64_t tick_jump_limit; 1329 uint64_t mondo_time_limit; 1330 uint64_t func_time_limit; 1331 uint64_t scale; 1332 1333 uint64_t latency; /* nanoseconds */ 1334 uint64_t maxfreq; 1335 uint64_t tick_limit_save = xc_tick_limit; 1336 uint64_t sync_tick_limit_save = xc_sync_tick_limit; 1337 uint_t tick_scale; 1338 uint64_t top; 1339 uint64_t bottom; 1340 u_number tk; 1341 1342 md_t *mdp; 1343 int nrnode; 1344 mde_cookie_t *platlist; 1345 1346 /* 1347 * Look up the 'inter-cpu-latency' (optional) property in the 1348 * platform node of the MD. The units are nanoseconds. 1349 */ 1350 if ((mdp = md_get_handle()) == NULL) { 1351 cmn_err(CE_WARN, "recalc_xc_timeouts: " 1352 "Unable to initialize machine description"); 1353 return; 1354 } 1355 1356 nrnode = md_alloc_scan_dag(mdp, 1357 md_root_node(mdp), "platform", "fwd", &platlist); 1358 1359 ASSERT(nrnode == 1); 1360 if (nrnode < 1) { 1361 cmn_err(CE_WARN, "recalc_xc_timeouts: platform node missing"); 1362 goto done; 1363 } 1364 if (md_get_prop_val(mdp, platlist[0], 1365 "inter-cpu-latency", &latency) == -1) 1366 goto done; 1367 1368 /* 1369 * clock.h defines an assembly-language macro 1370 * (NATIVE_TIME_TO_NSEC_SCALE) to convert from %stick 1371 * units to nanoseconds. Since the inter-cpu-latency 1372 * units are nanoseconds and the xc_* variables require 1373 * %stick units, we need the inverse of that function. 1374 * The trick is to perform the calculation without 1375 * floating point, but also without integer truncation 1376 * or overflow. To understand the calculation below, 1377 * please read the discussion of the macro in clock.h. 1378 * Since this new code will be invoked infrequently, 1379 * we can afford to implement it in C. 1380 * 1381 * tick_scale is the reciprocal of nsec_scale which is 1382 * calculated at startup in setcpudelay(). The calc 1383 * of tick_limit parallels that of NATIVE_TIME_TO_NSEC_SCALE 1384 * except we use tick_scale instead of nsec_scale and 1385 * C instead of assembler. 1386 */ 1387 tick_scale = (uint_t)(((u_longlong_t)sys_tick_freq 1388 << (32 - nsec_shift)) / NANOSEC); 1389 1390 tk.whole = latency; 1391 top = ((uint64_t)tk.half.high << 4) * tick_scale; 1392 bottom = (((uint64_t)tk.half.low << 4) * (uint64_t)tick_scale) >> 32; 1393 tick_limit = top + bottom; 1394 1395 /* 1396 * xc_init() calculated 'maxfreq' by looking at all the cpus, 1397 * and used it to derive some of the timeout variables that we 1398 * recalculate below. We can back into the original value by 1399 * using the inverse of one of those calculations. 1400 */ 1401 maxfreq = xc_mondo_time_limit / xc_scale; 1402 1403 /* 1404 * Don't allow the new timeout (xc_tick_limit) to fall below 1405 * the system tick frequency (stick). Allowing the timeout 1406 * to be set more tightly than this empirically determined 1407 * value may cause panics. 1408 */ 1409 tick_limit = tick_limit < sys_tick_freq ? sys_tick_freq : tick_limit; 1410 1411 tick_jump_limit = tick_limit / 32; 1412 tick_limit *= xc_tick_limit_scale; 1413 1414 /* 1415 * Recalculate xc_scale since it is used in a callback function 1416 * (xc_func_timeout_adj) to adjust two of the timeouts dynamically. 1417 * Make the change in xc_scale proportional to the change in 1418 * xc_tick_limit. 1419 */ 1420 scale = (xc_scale * tick_limit + sys_tick_freq / 2) / tick_limit_save; 1421 if (scale == 0) 1422 scale = 1; 1423 1424 mondo_time_limit = maxfreq * scale; 1425 func_time_limit = mondo_time_limit * xc_mondo_multiplier; 1426 1427 /* 1428 * Don't modify the timeouts if nothing has changed. Else, 1429 * stuff the variables with the freshly calculated (temp) 1430 * variables. This minimizes the window where the set of 1431 * values could be inconsistent. 1432 */ 1433 if (tick_limit != xc_tick_limit) { 1434 xc_tick_limit = tick_limit; 1435 xc_tick_jump_limit = tick_jump_limit; 1436 xc_scale = scale; 1437 xc_mondo_time_limit = mondo_time_limit; 1438 xc_func_time_limit = func_time_limit; 1439 } 1440 1441 done: 1442 /* 1443 * Increase the timeout limit for xt_sync() cross calls. 1444 */ 1445 xc_sync_tick_limit = xc_tick_limit * (cpu_q_entries / QFACTOR); 1446 xc_sync_tick_limit = xc_sync_tick_limit < xc_tick_limit ? 1447 xc_tick_limit : xc_sync_tick_limit; 1448 1449 /* 1450 * Force the new values to be used for future cross calls. 1451 * This is necessary only when we increase the timeouts. 1452 */ 1453 if ((xc_tick_limit > tick_limit_save) || (xc_sync_tick_limit > 1454 sync_tick_limit_save)) { 1455 cpuset_t cpuset = cpu_ready_set; 1456 xt_sync(cpuset); 1457 } 1458 1459 if (nrnode > 0) 1460 md_free_scan_dag(mdp, &platlist); 1461 (void) md_fini_handle(mdp); 1462 } 1463 1464 void 1465 mach_soft_state_init(void) 1466 { 1467 int i; 1468 uint64_t ra; 1469 1470 /* 1471 * Try to register soft_state api. If it fails, soft_state api has not 1472 * been implemented in the firmware, so do not bother to setup 1473 * soft_state in the kernel. 1474 */ 1475 if ((i = hsvc_register(&soft_state_hsvc, &soft_state_sup_minor)) != 0) { 1476 return; 1477 } 1478 for (i = 0; i < SOLARIS_SOFT_STATE_MSG_CNT; i++) { 1479 ASSERT(strlen((const char *)(void *) 1480 soft_state_message_strings + i) < SSM_SIZE); 1481 if ((ra = va_to_pa( 1482 (void *)(soft_state_message_strings + i))) == -1ll) { 1483 return; 1484 } 1485 soft_state_message_ra[i] = ra; 1486 } 1487 /* 1488 * Tell OBP that we are supporting Guest State 1489 */ 1490 prom_sun4v_soft_state_supported(); 1491 soft_state_initialized = 1; 1492 } 1493 1494 void 1495 mach_set_soft_state(uint64_t state, uint64_t *string_ra) 1496 { 1497 uint64_t rc; 1498 1499 if (soft_state_initialized && *string_ra) { 1500 rc = hv_soft_state_set(state, *string_ra); 1501 if (rc != H_EOK) { 1502 cmn_err(CE_WARN, 1503 "hv_soft_state_set returned %ld\n", rc); 1504 } 1505 } 1506 } 1507 1508 void 1509 mach_get_soft_state(uint64_t *state, uint64_t *string_ra) 1510 { 1511 uint64_t rc; 1512 1513 if (soft_state_initialized && *string_ra) { 1514 rc = hv_soft_state_get(*string_ra, state); 1515 if (rc != H_EOK) { 1516 cmn_err(CE_WARN, 1517 "hv_soft_state_get returned %ld\n", rc); 1518 *state = -1; 1519 } 1520 } 1521 } 1522