1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/archsystm.h> 31 #include <sys/t_lock.h> 32 #include <sys/uadmin.h> 33 #include <sys/panic.h> 34 #include <sys/reboot.h> 35 #include <sys/autoconf.h> 36 #include <sys/machsystm.h> 37 #include <sys/promif.h> 38 #include <sys/membar.h> 39 #include <vm/hat_sfmmu.h> 40 #include <sys/cpu_module.h> 41 #include <sys/cpu_sgnblk_defs.h> 42 #include <sys/intreg.h> 43 #include <sys/consdev.h> 44 #include <sys/kdi_impl.h> 45 #include <sys/traptrace.h> 46 #include <sys/hypervisor_api.h> 47 #include <sys/vmsystm.h> 48 #include <sys/dtrace.h> 49 #include <sys/xc_impl.h> 50 #include <sys/callb.h> 51 #include <sys/mdesc.h> 52 #include <sys/mach_descrip.h> 53 #include <sys/wdt.h> 54 #include <sys/soft_state.h> 55 #include <sys/promimpl.h> 56 #include <sys/hsvc.h> 57 #include <sys/ldoms.h> 58 59 /* 60 * hvdump_buf_va is a pointer to the currently-configured hvdump_buf. 61 * A value of NULL indicates that this area is not configured. 62 * hvdump_buf_sz is tunable but will be clamped to HVDUMP_SIZE_MAX. 63 */ 64 65 caddr_t hvdump_buf_va; 66 uint64_t hvdump_buf_sz = HVDUMP_SIZE_DEFAULT; 67 static uint64_t hvdump_buf_pa; 68 69 u_longlong_t panic_tick; 70 71 extern u_longlong_t gettick(); 72 static void reboot_machine(char *); 73 static void update_hvdump_buffer(void); 74 75 /* 76 * For xt_sync synchronization. 77 */ 78 extern uint64_t xc_tick_limit; 79 extern uint64_t xc_tick_jump_limit; 80 81 /* 82 * We keep our own copies, used for cache flushing, because we can be called 83 * before cpu_fiximpl(). 84 */ 85 static int kdi_dcache_size; 86 static int kdi_dcache_linesize; 87 static int kdi_icache_size; 88 static int kdi_icache_linesize; 89 90 /* 91 * Assembly support for generic modules in sun4v/ml/mach_xc.s 92 */ 93 extern void init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2); 94 extern void kdi_flush_idcache(int, int, int, int); 95 extern uint64_t get_cpuaddr(uint64_t, uint64_t); 96 97 98 #define BOOT_CMD_MAX_LEN 256 99 #define BOOT_CMD_BASE "boot " 100 101 /* 102 * In an LDoms system we do not save the user's boot args in NVRAM 103 * as is done on legacy systems. Instead, we format and send a 104 * 'reboot-command' variable to the variable service. The contents 105 * of the variable are retrieved by OBP and used verbatim for 106 * the next boot. 107 */ 108 static void 109 store_boot_cmd(char *args, boolean_t add_boot_str) 110 { 111 static char cmd_buf[BOOT_CMD_MAX_LEN]; 112 size_t len = 1; 113 pnode_t node; 114 size_t base_len = 0; 115 size_t args_len; 116 size_t args_max; 117 118 if (add_boot_str) { 119 (void) strcpy(cmd_buf, BOOT_CMD_BASE); 120 121 base_len = strlen(BOOT_CMD_BASE); 122 len = base_len + 1; 123 } 124 125 if (args != NULL) { 126 args_len = strlen(args); 127 args_max = BOOT_CMD_MAX_LEN - len; 128 129 if (args_len > args_max) { 130 cmn_err(CE_WARN, "Reboot command too long (%ld), " 131 "truncating command arguments", len + args_len); 132 133 args_len = args_max; 134 } 135 136 len += args_len; 137 (void) strncpy(&cmd_buf[base_len], args, args_len); 138 } 139 140 node = prom_optionsnode(); 141 if ((node == OBP_NONODE) || (node == OBP_BADNODE) || 142 prom_setprop(node, "reboot-command", cmd_buf, len) == -1) 143 cmn_err(CE_WARN, "Unable to store boot command for " 144 "use on reboot"); 145 } 146 147 148 /* 149 * Machine dependent code to reboot. 150 * 151 * "bootstr", when non-null, points to a string to be used as the 152 * argument string when rebooting. 153 * 154 * "invoke_cb" is a boolean. It is set to true when mdboot() can safely 155 * invoke CB_CL_MDBOOT callbacks before shutting the system down, i.e. when 156 * we are in a normal shutdown sequence (interrupts are not blocked, the 157 * system is not panic'ing or being suspended). 158 */ 159 /*ARGSUSED*/ 160 void 161 mdboot(int cmd, int fcn, char *bootstr, boolean_t invoke_cb) 162 { 163 extern void pm_cfb_check_and_powerup(void); 164 165 /* 166 * XXX - rconsvp is set to NULL to ensure that output messages 167 * are sent to the underlying "hardware" device using the 168 * monitor's printf routine since we are in the process of 169 * either rebooting or halting the machine. 170 */ 171 rconsvp = NULL; 172 173 switch (fcn) { 174 case AD_HALT: 175 /* 176 * LDoms: By storing a no-op command 177 * in the 'reboot-command' variable we cause OBP 178 * to ignore the setting of 'auto-boot?' after 179 * it completes the reset. This causes the system 180 * to stop at the ok prompt. 181 */ 182 if (domaining_enabled() && invoke_cb) 183 store_boot_cmd("noop", B_FALSE); 184 break; 185 186 case AD_POWEROFF: 187 break; 188 189 default: 190 if (bootstr == NULL) { 191 switch (fcn) { 192 193 case AD_BOOT: 194 bootstr = ""; 195 break; 196 197 case AD_IBOOT: 198 bootstr = "-a"; 199 break; 200 201 case AD_SBOOT: 202 bootstr = "-s"; 203 break; 204 205 case AD_SIBOOT: 206 bootstr = "-sa"; 207 break; 208 default: 209 cmn_err(CE_WARN, 210 "mdboot: invalid function %d", fcn); 211 bootstr = ""; 212 break; 213 } 214 } 215 216 /* 217 * If LDoms is running, we must save the boot string 218 * before we enter restricted mode. This is possible 219 * only if we are not being called from panic. 220 */ 221 if (domaining_enabled() && invoke_cb) 222 store_boot_cmd(bootstr, B_TRUE); 223 } 224 225 /* 226 * At a high interrupt level we can't: 227 * 1) bring up the console 228 * or 229 * 2) wait for pending interrupts prior to redistribution 230 * to the current CPU 231 * 232 * so we do them now. 233 */ 234 pm_cfb_check_and_powerup(); 235 236 /* make sure there are no more changes to the device tree */ 237 devtree_freeze(); 238 239 if (invoke_cb) 240 (void) callb_execute_class(CB_CL_MDBOOT, NULL); 241 242 /* 243 * Clear any unresolved UEs from memory. 244 */ 245 page_retire_mdboot(); 246 247 /* 248 * stop other cpus which also raise our priority. since there is only 249 * one active cpu after this, and our priority will be too high 250 * for us to be preempted, we're essentially single threaded 251 * from here on out. 252 */ 253 stop_other_cpus(); 254 255 /* 256 * try and reset leaf devices. reset_leaves() should only 257 * be called when there are no other threads that could be 258 * accessing devices 259 */ 260 reset_leaves(); 261 262 watchdog_clear(); 263 264 if (fcn == AD_HALT) { 265 mach_set_soft_state(SIS_TRANSITION, 266 &SOLARIS_SOFT_STATE_HALT_MSG); 267 halt((char *)NULL); 268 } else if (fcn == AD_POWEROFF) { 269 mach_set_soft_state(SIS_TRANSITION, 270 &SOLARIS_SOFT_STATE_POWER_MSG); 271 power_down(NULL); 272 } else { 273 mach_set_soft_state(SIS_TRANSITION, 274 &SOLARIS_SOFT_STATE_REBOOT_MSG); 275 reboot_machine(bootstr); 276 } 277 /* MAYBE REACHED */ 278 } 279 280 /* mdpreboot - may be called prior to mdboot while root fs still mounted */ 281 /*ARGSUSED*/ 282 void 283 mdpreboot(int cmd, int fcn, char *bootstr) 284 { 285 } 286 287 /* 288 * Halt the machine and then reboot with the device 289 * and arguments specified in bootstr. 290 */ 291 static void 292 reboot_machine(char *bootstr) 293 { 294 flush_windows(); 295 stop_other_cpus(); /* send stop signal to other CPUs */ 296 prom_printf("rebooting...\n"); 297 /* 298 * For platforms that use CPU signatures, we 299 * need to set the signature block to OS and 300 * the state to exiting for all the processors. 301 */ 302 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_REBOOT, -1); 303 prom_reboot(bootstr); 304 /*NOTREACHED*/ 305 } 306 307 /* 308 * We use the x-trap mechanism and idle_stop_xcall() to stop the other CPUs. 309 * Once in panic_idle() they raise spl, record their location, and spin. 310 */ 311 static void 312 panic_idle(void) 313 { 314 (void) spl7(); 315 316 debug_flush_windows(); 317 (void) setjmp(&curthread->t_pcb); 318 319 CPU->cpu_m.in_prom = 1; 320 membar_stld(); 321 322 for (;;) 323 ; 324 } 325 326 /* 327 * Force the other CPUs to trap into panic_idle(), and then remove them 328 * from the cpu_ready_set so they will no longer receive cross-calls. 329 */ 330 /*ARGSUSED*/ 331 void 332 panic_stopcpus(cpu_t *cp, kthread_t *t, int spl) 333 { 334 cpuset_t cps; 335 int i; 336 337 (void) splzs(); 338 CPUSET_ALL_BUT(cps, cp->cpu_id); 339 xt_some(cps, (xcfunc_t *)idle_stop_xcall, (uint64_t)&panic_idle, NULL); 340 341 for (i = 0; i < NCPU; i++) { 342 if (i != cp->cpu_id && CPU_XCALL_READY(i)) { 343 int ntries = 0x10000; 344 345 while (!cpu[i]->cpu_m.in_prom && ntries) { 346 DELAY(50); 347 ntries--; 348 } 349 350 if (!cpu[i]->cpu_m.in_prom) 351 printf("panic: failed to stop cpu%d\n", i); 352 353 cpu[i]->cpu_flags &= ~CPU_READY; 354 cpu[i]->cpu_flags |= CPU_QUIESCED; 355 CPUSET_DEL(cpu_ready_set, cpu[i]->cpu_id); 356 } 357 } 358 } 359 360 /* 361 * Platform callback following each entry to panicsys(). If we've panicked at 362 * level 14, we examine t_panic_trap to see if a fatal trap occurred. If so, 363 * we disable further %tick_cmpr interrupts. If not, an explicit call to panic 364 * was made and so we re-enqueue an interrupt request structure to allow 365 * further level 14 interrupts to be processed once we lower PIL. This allows 366 * us to handle panics from the deadman() CY_HIGH_LEVEL cyclic. 367 */ 368 void 369 panic_enter_hw(int spl) 370 { 371 if (!panic_tick) { 372 panic_tick = gettick(); 373 if (mach_htraptrace_enable) { 374 uint64_t prev_freeze; 375 376 /* there are no possible error codes for this hcall */ 377 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 378 &prev_freeze); 379 } 380 #ifdef TRAPTRACE 381 TRAPTRACE_FREEZE; 382 #endif 383 } 384 385 mach_set_soft_state(SIS_TRANSITION, &SOLARIS_SOFT_STATE_PANIC_MSG); 386 387 if (spl == ipltospl(PIL_14)) { 388 uint_t opstate = disable_vec_intr(); 389 390 if (curthread->t_panic_trap != NULL) { 391 tickcmpr_disable(); 392 intr_dequeue_req(PIL_14, cbe_level14_inum); 393 } else { 394 if (!tickcmpr_disabled()) 395 intr_enqueue_req(PIL_14, cbe_level14_inum); 396 /* 397 * Clear SOFTINT<14>, SOFTINT<0> (TICK_INT) 398 * and SOFTINT<16> (STICK_INT) to indicate 399 * that the current level 14 has been serviced. 400 */ 401 wr_clr_softint((1 << PIL_14) | 402 TICK_INT_MASK | STICK_INT_MASK); 403 } 404 405 enable_vec_intr(opstate); 406 } 407 } 408 409 /* 410 * Miscellaneous hardware-specific code to execute after panicstr is set 411 * by the panic code: we also print and record PTL1 panic information here. 412 */ 413 /*ARGSUSED*/ 414 void 415 panic_quiesce_hw(panic_data_t *pdp) 416 { 417 extern uint_t getpstate(void); 418 extern void setpstate(uint_t); 419 420 /* 421 * Turn off TRAPTRACE and save the current %tick value in panic_tick. 422 */ 423 if (!panic_tick) { 424 panic_tick = gettick(); 425 if (mach_htraptrace_enable) { 426 uint64_t prev_freeze; 427 428 /* there are no possible error codes for this hcall */ 429 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 430 &prev_freeze); 431 } 432 #ifdef TRAPTRACE 433 TRAPTRACE_FREEZE; 434 #endif 435 } 436 /* 437 * For Platforms that use CPU signatures, we 438 * need to set the signature block to OS, the state to 439 * exiting, and the substate to panic for all the processors. 440 */ 441 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_PANIC, -1); 442 443 update_hvdump_buffer(); 444 445 /* 446 * Disable further ECC errors from the bus nexus. 447 */ 448 (void) bus_func_invoke(BF_TYPE_ERRDIS); 449 450 /* 451 * Redirect all interrupts to the current CPU. 452 */ 453 intr_redist_all_cpus_shutdown(); 454 455 /* 456 * This call exists solely to support dumps to network 457 * devices after sync from OBP. 458 * 459 * If we came here via the sync callback, then on some 460 * platforms, interrupts may have arrived while we were 461 * stopped in OBP. OBP will arrange for those interrupts to 462 * be redelivered if you say "go", but not if you invoke a 463 * client callback like 'sync'. For some dump devices 464 * (network swap devices), we need interrupts to be 465 * delivered in order to dump, so we have to call the bus 466 * nexus driver to reset the interrupt state machines. 467 */ 468 (void) bus_func_invoke(BF_TYPE_RESINTR); 469 470 setpstate(getpstate() | PSTATE_IE); 471 } 472 473 /* 474 * Platforms that use CPU signatures need to set the signature block to OS and 475 * the state to exiting for all CPUs. PANIC_CONT indicates that we're about to 476 * write the crash dump, which tells the SSP/SMS to begin a timeout routine to 477 * reboot the machine if the dump never completes. 478 */ 479 /*ARGSUSED*/ 480 void 481 panic_dump_hw(int spl) 482 { 483 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_DUMP, -1); 484 } 485 486 /* 487 * for ptl1_panic 488 */ 489 void 490 ptl1_init_cpu(struct cpu *cpu) 491 { 492 ptl1_state_t *pstate = &cpu->cpu_m.ptl1_state; 493 494 /*CONSTCOND*/ 495 if (sizeof (struct cpu) + PTL1_SSIZE > CPU_ALLOC_SIZE) { 496 panic("ptl1_init_cpu: not enough space left for ptl1_panic " 497 "stack, sizeof (struct cpu) = %lu", 498 (unsigned long)sizeof (struct cpu)); 499 } 500 501 pstate->ptl1_stktop = (uintptr_t)cpu + CPU_ALLOC_SIZE; 502 cpu_pa[cpu->cpu_id] = va_to_pa(cpu); 503 } 504 505 void 506 ptl1_panic_handler(ptl1_state_t *pstate) 507 { 508 static const char *ptl1_reasons[] = { 509 #ifdef PTL1_PANIC_DEBUG 510 "trap for debug purpose", /* PTL1_BAD_DEBUG */ 511 #else 512 "unknown trap", /* PTL1_BAD_DEBUG */ 513 #endif 514 "register window trap", /* PTL1_BAD_WTRAP */ 515 "kernel MMU miss", /* PTL1_BAD_KMISS */ 516 "kernel protection fault", /* PTL1_BAD_KPROT_FAULT */ 517 "ISM MMU miss", /* PTL1_BAD_ISM */ 518 "kernel MMU trap", /* PTL1_BAD_MMUTRAP */ 519 "kernel trap handler state", /* PTL1_BAD_TRAP */ 520 "floating point trap", /* PTL1_BAD_FPTRAP */ 521 #ifdef DEBUG 522 "pointer to intr_vec", /* PTL1_BAD_INTR_VEC */ 523 #else 524 "unknown trap", /* PTL1_BAD_INTR_VEC */ 525 #endif 526 #ifdef TRAPTRACE 527 "TRACE_PTR state", /* PTL1_BAD_TRACE_PTR */ 528 #else 529 "unknown trap", /* PTL1_BAD_TRACE_PTR */ 530 #endif 531 "stack overflow", /* PTL1_BAD_STACK */ 532 "DTrace flags", /* PTL1_BAD_DTRACE_FLAGS */ 533 "attempt to steal locked ctx", /* PTL1_BAD_CTX_STEAL */ 534 "CPU ECC error loop", /* PTL1_BAD_ECC */ 535 "unexpected error from hypervisor call", /* PTL1_BAD_HCALL */ 536 "unexpected global level(%gl)", /* PTL1_BAD_GL */ 537 "Watchdog Reset", /* PTL1_BAD_WATCHDOG */ 538 "unexpected RED mode trap", /* PTL1_BAD_RED */ 539 "return value EINVAL from hcall: "\ 540 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_EINVAL */ 541 "return value ENOMAP from hcall: "\ 542 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_ENOMAP */ 543 "error raising a TSB exception", /* PTL1_BAD_RAISE_TSBEXCP */ 544 "missing shared TSB" /* PTL1_NO_SCDTSB8K */ 545 }; 546 547 uint_t reason = pstate->ptl1_regs.ptl1_gregs[0].ptl1_g1; 548 uint_t tl = pstate->ptl1_regs.ptl1_trap_regs[0].ptl1_tl; 549 struct panic_trap_info ti = { 0 }; 550 551 /* 552 * Use trap_info for a place holder to call panic_savetrap() and 553 * panic_showtrap() to save and print out ptl1_panic information. 554 */ 555 if (curthread->t_panic_trap == NULL) 556 curthread->t_panic_trap = &ti; 557 558 if (reason < sizeof (ptl1_reasons) / sizeof (ptl1_reasons[0])) 559 panic("bad %s at TL %u", ptl1_reasons[reason], tl); 560 else 561 panic("ptl1_panic reason 0x%x at TL %u", reason, tl); 562 } 563 564 void 565 clear_watchdog_on_exit(void) 566 { 567 if (watchdog_enabled && watchdog_activated) { 568 prom_printf("Debugging requested; hardware watchdog " 569 "suspended.\n"); 570 (void) watchdog_suspend(); 571 } 572 } 573 574 /* 575 * Restore the watchdog timer when returning from a debugger 576 * after a panic or L1-A and resume watchdog pat. 577 */ 578 void 579 restore_watchdog_on_entry() 580 { 581 watchdog_resume(); 582 } 583 584 int 585 kdi_watchdog_disable(void) 586 { 587 watchdog_suspend(); 588 589 return (0); 590 } 591 592 void 593 kdi_watchdog_restore(void) 594 { 595 watchdog_resume(); 596 } 597 598 void 599 mach_dump_buffer_init(void) 600 { 601 uint64_t ret, minsize = 0; 602 603 if (hvdump_buf_sz > HVDUMP_SIZE_MAX) 604 hvdump_buf_sz = HVDUMP_SIZE_MAX; 605 606 hvdump_buf_va = contig_mem_alloc_align(hvdump_buf_sz, PAGESIZE); 607 if (hvdump_buf_va == NULL) 608 return; 609 610 hvdump_buf_pa = va_to_pa(hvdump_buf_va); 611 612 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 613 &minsize); 614 615 if (ret != H_EOK) { 616 contig_mem_free(hvdump_buf_va, hvdump_buf_sz); 617 hvdump_buf_va = NULL; 618 cmn_err(CE_NOTE, "!Error in setting up hvstate" 619 "dump buffer. Error = 0x%lx, size = 0x%lx," 620 "buf_pa = 0x%lx", ret, hvdump_buf_sz, 621 hvdump_buf_pa); 622 623 if (ret == H_EINVAL) { 624 cmn_err(CE_NOTE, "!Buffer size too small." 625 "Available buffer size = 0x%lx," 626 "Minimum buffer size required = 0x%lx", 627 hvdump_buf_sz, minsize); 628 } 629 } 630 } 631 632 633 static void 634 update_hvdump_buffer(void) 635 { 636 uint64_t ret, dummy_val; 637 638 if (hvdump_buf_va == NULL) 639 return; 640 641 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 642 &dummy_val); 643 if (ret != H_EOK) { 644 cmn_err(CE_NOTE, "!Cannot update hvstate dump" 645 "buffer. Error = 0x%lx", ret); 646 } 647 } 648 649 650 static int 651 getintprop(pnode_t node, char *name, int deflt) 652 { 653 int value; 654 655 switch (prom_getproplen(node, name)) { 656 case 0: 657 value = 1; /* boolean properties */ 658 break; 659 660 case sizeof (int): 661 (void) prom_getprop(node, name, (caddr_t)&value); 662 break; 663 664 default: 665 value = deflt; 666 break; 667 } 668 669 return (value); 670 } 671 672 /* 673 * Called by setcpudelay 674 */ 675 void 676 cpu_init_tick_freq(void) 677 { 678 md_t *mdp; 679 mde_cookie_t rootnode; 680 int listsz; 681 mde_cookie_t *listp = NULL; 682 int num_nodes; 683 uint64_t stick_prop; 684 685 if (broken_md_flag) { 686 sys_tick_freq = cpunodes[CPU->cpu_id].clock_freq; 687 return; 688 } 689 690 if ((mdp = md_get_handle()) == NULL) 691 panic("stick_frequency property not found in MD"); 692 693 rootnode = md_root_node(mdp); 694 ASSERT(rootnode != MDE_INVAL_ELEM_COOKIE); 695 696 num_nodes = md_node_count(mdp); 697 698 ASSERT(num_nodes > 0); 699 listsz = num_nodes * sizeof (mde_cookie_t); 700 listp = (mde_cookie_t *)prom_alloc((caddr_t)0, listsz, 0); 701 702 if (listp == NULL) 703 panic("cannot allocate list for MD properties"); 704 705 num_nodes = md_scan_dag(mdp, rootnode, md_find_name(mdp, "platform"), 706 md_find_name(mdp, "fwd"), listp); 707 708 ASSERT(num_nodes == 1); 709 710 if (md_get_prop_val(mdp, *listp, "stick-frequency", &stick_prop) != 0) 711 panic("stick_frequency property not found in MD"); 712 713 sys_tick_freq = stick_prop; 714 715 prom_free((caddr_t)listp, listsz); 716 (void) md_fini_handle(mdp); 717 } 718 719 int shipit(int n, uint64_t cpu_list_ra); 720 extern uint64_t xc_tick_limit; 721 extern uint64_t xc_tick_jump_limit; 722 723 #ifdef DEBUG 724 #define SEND_MONDO_STATS 1 725 #endif 726 727 #ifdef SEND_MONDO_STATS 728 uint32_t x_one_stimes[64]; 729 uint32_t x_one_ltimes[16]; 730 uint32_t x_set_stimes[64]; 731 uint32_t x_set_ltimes[16]; 732 uint32_t x_set_cpus[NCPU]; 733 #endif 734 735 void 736 send_one_mondo(int cpuid) 737 { 738 int retries, stat; 739 uint64_t starttick, endtick, tick, lasttick; 740 struct machcpu *mcpup = &(CPU->cpu_m); 741 742 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 743 starttick = lasttick = gettick(); 744 mcpup->cpu_list[0] = (uint16_t)cpuid; 745 stat = shipit(1, mcpup->cpu_list_ra); 746 endtick = starttick + xc_tick_limit; 747 retries = 0; 748 while (stat != H_EOK) { 749 if (stat != H_EWOULDBLOCK) { 750 if (panic_quiesce) 751 return; 752 if (stat == H_ECPUERROR) 753 cmn_err(CE_PANIC, "send_one_mondo: " 754 "cpuid: 0x%x has been marked in " 755 "error", cpuid); 756 else 757 cmn_err(CE_PANIC, "send_one_mondo: " 758 "unexpected hypervisor error 0x%x " 759 "while sending a mondo to cpuid: " 760 "0x%x", stat, cpuid); 761 } 762 tick = gettick(); 763 /* 764 * If there is a big jump between the current tick 765 * count and lasttick, we have probably hit a break 766 * point. Adjust endtick accordingly to avoid panic. 767 */ 768 if (tick > (lasttick + xc_tick_jump_limit)) 769 endtick += (tick - lasttick); 770 lasttick = tick; 771 if (tick > endtick) { 772 if (panic_quiesce) 773 return; 774 cmn_err(CE_PANIC, "send mondo timeout " 775 "(target 0x%x) [retries: 0x%x hvstat: 0x%x]", 776 cpuid, retries, stat); 777 } 778 drv_usecwait(1); 779 stat = shipit(1, mcpup->cpu_list_ra); 780 retries++; 781 } 782 #ifdef SEND_MONDO_STATS 783 { 784 uint64_t n = gettick() - starttick; 785 if (n < 8192) 786 x_one_stimes[n >> 7]++; 787 else if (n < 15*8192) 788 x_one_ltimes[n >> 13]++; 789 else 790 x_one_ltimes[0xf]++; 791 } 792 #endif 793 } 794 795 void 796 send_mondo_set(cpuset_t set) 797 { 798 uint64_t starttick, endtick, tick, lasttick; 799 uint_t largestid, smallestid; 800 int i, j; 801 int ncpuids = 0; 802 int shipped = 0; 803 int retries = 0; 804 struct machcpu *mcpup = &(CPU->cpu_m); 805 806 ASSERT(!CPUSET_ISNULL(set)); 807 CPUSET_BOUNDS(set, smallestid, largestid); 808 if (smallestid == CPUSET_NOTINSET) { 809 return; 810 } 811 812 starttick = lasttick = gettick(); 813 endtick = starttick + xc_tick_limit; 814 815 /* 816 * Assemble CPU list for HV argument. We already know 817 * smallestid and largestid are members of set. 818 */ 819 mcpup->cpu_list[ncpuids++] = (uint16_t)smallestid; 820 if (largestid != smallestid) { 821 for (i = smallestid+1; i <= largestid-1; i++) { 822 if (CPU_IN_SET(set, i)) { 823 mcpup->cpu_list[ncpuids++] = (uint16_t)i; 824 } 825 } 826 mcpup->cpu_list[ncpuids++] = (uint16_t)largestid; 827 } 828 829 do { 830 int stat; 831 832 stat = shipit(ncpuids, mcpup->cpu_list_ra); 833 if (stat == H_EOK) { 834 shipped += ncpuids; 835 break; 836 } 837 838 /* 839 * Either not all CPU mondos were sent, or an 840 * error occurred. CPUs that were sent mondos 841 * have their CPU IDs overwritten in cpu_list. 842 * Reset cpu_list so that it only holds those 843 * CPU IDs that still need to be sent. 844 */ 845 for (i = 0, j = 0; i < ncpuids; i++) { 846 if (mcpup->cpu_list[i] == HV_SEND_MONDO_ENTRYDONE) { 847 shipped++; 848 } else { 849 mcpup->cpu_list[j++] = mcpup->cpu_list[i]; 850 } 851 } 852 ncpuids = j; 853 854 /* 855 * Now handle possible errors returned 856 * from hypervisor. 857 */ 858 if (stat == H_ECPUERROR) { 859 int errorcpus; 860 861 if (!panic_quiesce) 862 cmn_err(CE_CONT, "send_mondo_set: cpuid(s) "); 863 864 /* 865 * Remove any CPUs in the error state from 866 * cpu_list. At this point cpu_list only 867 * contains the CPU IDs for mondos not 868 * succesfully sent. 869 */ 870 for (i = 0, errorcpus = 0; i < ncpuids; i++) { 871 uint64_t state = CPU_STATE_INVALID; 872 uint16_t id = mcpup->cpu_list[i]; 873 874 (void) hv_cpu_state(id, &state); 875 if (state == CPU_STATE_ERROR) { 876 if (!panic_quiesce) 877 cmn_err(CE_CONT, "0x%x ", id); 878 errorcpus++; 879 } else if (errorcpus > 0) { 880 mcpup->cpu_list[i - errorcpus] = 881 mcpup->cpu_list[i]; 882 } 883 } 884 ncpuids -= errorcpus; 885 886 if (!panic_quiesce) { 887 if (errorcpus == 0) { 888 cmn_err(CE_CONT, "<none> have been " 889 "marked in error\n"); 890 cmn_err(CE_PANIC, "send_mondo_set: " 891 "hypervisor returned " 892 "H_ECPUERROR but no CPU in " 893 "cpu_list in error state"); 894 } else { 895 cmn_err(CE_CONT, "have been marked in " 896 "error\n"); 897 cmn_err(CE_PANIC, "send_mondo_set: " 898 "CPU(s) in error state"); 899 } 900 } 901 } else if (stat != H_EWOULDBLOCK) { 902 if (panic_quiesce) 903 return; 904 /* 905 * For all other errors, panic. 906 */ 907 cmn_err(CE_CONT, "send_mondo_set: unexpected " 908 "hypervisor error 0x%x while sending a " 909 "mondo to cpuid(s):", stat); 910 for (i = 0; i < ncpuids; i++) { 911 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 912 } 913 cmn_err(CE_CONT, "\n"); 914 cmn_err(CE_PANIC, "send_mondo_set: unexpected " 915 "hypervisor error"); 916 } 917 918 tick = gettick(); 919 /* 920 * If there is a big jump between the current tick 921 * count and lasttick, we have probably hit a break 922 * point. Adjust endtick accordingly to avoid panic. 923 */ 924 if (tick > (lasttick + xc_tick_jump_limit)) 925 endtick += (tick - lasttick); 926 lasttick = tick; 927 if (tick > endtick) { 928 if (panic_quiesce) 929 return; 930 cmn_err(CE_CONT, "send mondo timeout " 931 "[retries: 0x%x] cpuids: ", retries); 932 for (i = 0; i < ncpuids; i++) 933 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 934 cmn_err(CE_CONT, "\n"); 935 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 936 } 937 938 while (gettick() < (tick + sys_clock_mhz)) 939 ; 940 retries++; 941 } while (ncpuids > 0); 942 943 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 944 945 #ifdef SEND_MONDO_STATS 946 { 947 uint64_t n = gettick() - starttick; 948 if (n < 8192) 949 x_set_stimes[n >> 7]++; 950 else if (n < 15*8192) 951 x_set_ltimes[n >> 13]++; 952 else 953 x_set_ltimes[0xf]++; 954 } 955 x_set_cpus[shipped]++; 956 #endif 957 } 958 959 void 960 syncfpu(void) 961 { 962 } 963 964 void 965 sticksync_slave(void) 966 {} 967 968 void 969 sticksync_master(void) 970 {} 971 972 void 973 cpu_init_cache_scrub(void) 974 { 975 mach_set_soft_state(SIS_NORMAL, &SOLARIS_SOFT_STATE_RUN_MSG); 976 } 977 978 int 979 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 980 { 981 int ret, watched; 982 983 watched = watch_disable_addr((void *)addr, 4, S_WRITE); 984 ret = dtrace_blksuword32(addr, data, 0); 985 if (watched) 986 watch_enable_addr((void *)addr, 4, S_WRITE); 987 988 return (ret); 989 } 990 991 int 992 dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain) 993 { 994 if (suword32((void *)addr, *data) == -1) 995 return (tryagain ? dtrace_blksuword32_err(addr, data) : -1); 996 dtrace_flush_sec(addr); 997 998 return (0); 999 } 1000 1001 /*ARGSUSED*/ 1002 void 1003 cpu_faulted_enter(struct cpu *cp) 1004 { 1005 } 1006 1007 /*ARGSUSED*/ 1008 void 1009 cpu_faulted_exit(struct cpu *cp) 1010 { 1011 } 1012 1013 static int 1014 kdi_cpu_ready_iter(int (*cb)(int, void *), void *arg) 1015 { 1016 int rc, i; 1017 1018 for (rc = 0, i = 0; i < NCPU; i++) { 1019 if (CPU_IN_SET(cpu_ready_set, i)) 1020 rc += cb(i, arg); 1021 } 1022 1023 return (rc); 1024 } 1025 1026 /* 1027 * Sends a cross-call to a specified processor. The caller assumes 1028 * responsibility for repetition of cross-calls, as appropriate (MARSA for 1029 * debugging). 1030 */ 1031 static int 1032 kdi_xc_one(int cpuid, void (*func)(uintptr_t, uintptr_t), uintptr_t arg1, 1033 uintptr_t arg2) 1034 { 1035 int stat; 1036 struct machcpu *mcpup; 1037 uint64_t cpuaddr_reg = 0, cpuaddr_scr = 0; 1038 1039 mcpup = &(((cpu_t *)get_cpuaddr(cpuaddr_reg, cpuaddr_scr))->cpu_m); 1040 1041 /* 1042 * if (idsr_busy()) 1043 * return (KDI_XC_RES_ERR); 1044 */ 1045 1046 init_mondo_nocheck((xcfunc_t *)func, arg1, arg2); 1047 1048 mcpup->cpu_list[0] = (uint16_t)cpuid; 1049 stat = shipit(1, mcpup->cpu_list_ra); 1050 1051 if (stat == 0) 1052 return (KDI_XC_RES_OK); 1053 else 1054 return (KDI_XC_RES_NACK); 1055 } 1056 1057 static void 1058 kdi_tickwait(clock_t nticks) 1059 { 1060 clock_t endtick = gettick() + nticks; 1061 1062 while (gettick() < endtick) 1063 ; 1064 } 1065 1066 static void 1067 kdi_cpu_init(int dcache_size, int dcache_linesize, int icache_size, 1068 int icache_linesize) 1069 { 1070 kdi_dcache_size = dcache_size; 1071 kdi_dcache_linesize = dcache_linesize; 1072 kdi_icache_size = icache_size; 1073 kdi_icache_linesize = icache_linesize; 1074 } 1075 1076 /* used directly by kdi_read/write_phys */ 1077 void 1078 kdi_flush_caches(void) 1079 { 1080 /* Not required on sun4v architecture. */ 1081 } 1082 1083 /*ARGSUSED*/ 1084 int 1085 kdi_get_stick(uint64_t *stickp) 1086 { 1087 return (-1); 1088 } 1089 1090 void 1091 cpu_kdi_init(kdi_t *kdi) 1092 { 1093 kdi->kdi_flush_caches = kdi_flush_caches; 1094 kdi->mkdi_cpu_init = kdi_cpu_init; 1095 kdi->mkdi_cpu_ready_iter = kdi_cpu_ready_iter; 1096 kdi->mkdi_xc_one = kdi_xc_one; 1097 kdi->mkdi_tickwait = kdi_tickwait; 1098 kdi->mkdi_get_stick = kdi_get_stick; 1099 } 1100 1101 uint64_t soft_state_message_ra[SOLARIS_SOFT_STATE_MSG_CNT]; 1102 static uint64_t soft_state_saved_state = (uint64_t)-1; 1103 static int soft_state_initialized = 0; 1104 static uint64_t soft_state_sup_minor; /* Supported minor number */ 1105 static hsvc_info_t soft_state_hsvc = { 1106 HSVC_REV_1, NULL, HSVC_GROUP_SOFT_STATE, 1, 0, NULL }; 1107 1108 1109 static void 1110 sun4v_system_claim(void) 1111 { 1112 watchdog_suspend(); 1113 /* 1114 * For "mdb -K", set soft state to debugging 1115 */ 1116 if (soft_state_saved_state == -1) { 1117 mach_get_soft_state(&soft_state_saved_state, 1118 &SOLARIS_SOFT_STATE_SAVED_MSG); 1119 } 1120 /* 1121 * check again as the read above may or may not have worked and if 1122 * it didn't then soft state will still be -1 1123 */ 1124 if (soft_state_saved_state != -1) { 1125 mach_set_soft_state(SIS_TRANSITION, 1126 &SOLARIS_SOFT_STATE_DEBUG_MSG); 1127 } 1128 } 1129 1130 static void 1131 sun4v_system_release(void) 1132 { 1133 watchdog_resume(); 1134 /* 1135 * For "mdb -K", set soft_state state back to original state on exit 1136 */ 1137 if (soft_state_saved_state != -1) { 1138 mach_set_soft_state(soft_state_saved_state, 1139 &SOLARIS_SOFT_STATE_SAVED_MSG); 1140 soft_state_saved_state = -1; 1141 } 1142 } 1143 1144 void 1145 plat_kdi_init(kdi_t *kdi) 1146 { 1147 kdi->pkdi_system_claim = sun4v_system_claim; 1148 kdi->pkdi_system_release = sun4v_system_release; 1149 } 1150 1151 /* 1152 * Routine to return memory information associated 1153 * with a physical address and syndrome. 1154 */ 1155 /* ARGSUSED */ 1156 int 1157 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1158 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1159 int *segsp, int *banksp, int *mcidp) 1160 { 1161 return (ENOTSUP); 1162 } 1163 1164 /* 1165 * This routine returns the size of the kernel's FRU name buffer. 1166 */ 1167 size_t 1168 cpu_get_name_bufsize() 1169 { 1170 return (UNUM_NAMLEN); 1171 } 1172 1173 /* 1174 * This routine is a more generic interface to cpu_get_mem_unum(), 1175 * that may be used by other modules (e.g. mm). 1176 */ 1177 /* ARGSUSED */ 1178 int 1179 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1180 char *buf, int buflen, int *lenp) 1181 { 1182 return (ENOTSUP); 1183 } 1184 1185 /* ARGSUSED */ 1186 int 1187 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 1188 { 1189 return (ENOTSUP); 1190 } 1191 1192 /* ARGSUSED */ 1193 int 1194 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 1195 { 1196 return (ENOTSUP); 1197 } 1198 1199 /* 1200 * xt_sync - wait for previous x-traps to finish 1201 */ 1202 void 1203 xt_sync(cpuset_t cpuset) 1204 { 1205 union { 1206 uint8_t volatile byte[NCPU]; 1207 uint64_t volatile xword[NCPU / 8]; 1208 } cpu_sync; 1209 uint64_t starttick, endtick, tick, lasttick, traptrace_id; 1210 uint_t largestid, smallestid; 1211 int i, j; 1212 1213 kpreempt_disable(); 1214 CPUSET_DEL(cpuset, CPU->cpu_id); 1215 CPUSET_AND(cpuset, cpu_ready_set); 1216 1217 CPUSET_BOUNDS(cpuset, smallestid, largestid); 1218 if (smallestid == CPUSET_NOTINSET) 1219 goto out; 1220 1221 /* 1222 * Sun4v uses a queue for receiving mondos. Successful 1223 * transmission of a mondo only indicates that the mondo 1224 * has been written into the queue. 1225 * 1226 * We use an array of bytes to let each cpu to signal back 1227 * to the cross trap sender that the cross trap has been 1228 * executed. Set the byte to 1 before sending the cross trap 1229 * and wait until other cpus reset it to 0. 1230 */ 1231 bzero((void *)&cpu_sync, NCPU); 1232 cpu_sync.byte[smallestid] = 1; 1233 if (largestid != smallestid) { 1234 for (i = (smallestid + 1); i <= (largestid - 1); i++) 1235 if (CPU_IN_SET(cpuset, i)) 1236 cpu_sync.byte[i] = 1; 1237 cpu_sync.byte[largestid] = 1; 1238 } 1239 1240 /* 1241 * To help debug xt_sync panic, each mondo is uniquely identified 1242 * by passing the tick value, traptrace_id as the second mondo 1243 * argument to xt_some which is logged in CPU's mondo queue, 1244 * traptrace buffer and the panic message. 1245 */ 1246 traptrace_id = gettick(); 1247 xt_some(cpuset, (xcfunc_t *)xt_sync_tl1, 1248 (uint64_t)cpu_sync.byte, traptrace_id); 1249 1250 starttick = lasttick = gettick(); 1251 endtick = starttick + xc_tick_limit; 1252 1253 for (i = (smallestid / 8); i <= (largestid / 8); i++) { 1254 while (cpu_sync.xword[i] != 0) { 1255 tick = gettick(); 1256 /* 1257 * If there is a big jump between the current tick 1258 * count and lasttick, we have probably hit a break 1259 * point. Adjust endtick accordingly to avoid panic. 1260 */ 1261 if (tick > (lasttick + xc_tick_jump_limit)) { 1262 endtick += (tick - lasttick); 1263 } 1264 lasttick = tick; 1265 if (tick > endtick) { 1266 if (panic_quiesce) 1267 goto out; 1268 cmn_err(CE_CONT, "Cross trap sync timeout: " 1269 "at cpu_sync.xword[%d]: 0x%lx " 1270 "cpu_sync.byte: 0x%lx " 1271 "starttick: 0x%lx endtick: 0x%lx " 1272 "traptrace_id = 0x%lx\n", 1273 i, cpu_sync.xword[i], 1274 (uint64_t)cpu_sync.byte, 1275 starttick, endtick, traptrace_id); 1276 cmn_err(CE_CONT, "CPUIDs:"); 1277 for (j = (i * 8); j <= largestid; j++) { 1278 if (cpu_sync.byte[j] != 0) 1279 cmn_err(CE_CONT, " 0x%x", j); 1280 } 1281 cmn_err(CE_PANIC, "xt_sync: timeout"); 1282 } 1283 } 1284 } 1285 1286 out: 1287 kpreempt_enable(); 1288 } 1289 1290 /* 1291 * Recalculate the values of the cross-call timeout variables based 1292 * on the value of the 'inter-cpu-latency' property of the platform node. 1293 * The property sets the number of nanosec to wait for a cross-call 1294 * to be acknowledged. Other timeout variables are derived from it. 1295 * 1296 * N.B. This implementation is aware of the internals of xc_init() 1297 * and updates many of the same variables. 1298 */ 1299 void 1300 recalc_xc_timeouts(void) 1301 { 1302 typedef union { 1303 uint64_t whole; 1304 struct { 1305 uint_t high; 1306 uint_t low; 1307 } half; 1308 } u_number; 1309 1310 /* See x_call.c for descriptions of these extern variables. */ 1311 extern uint64_t xc_tick_limit_scale; 1312 extern uint64_t xc_mondo_time_limit; 1313 extern uint64_t xc_func_time_limit; 1314 extern uint64_t xc_scale; 1315 extern uint64_t xc_mondo_multiplier; 1316 extern uint_t nsec_shift; 1317 1318 /* Temp versions of the target variables */ 1319 uint64_t tick_limit; 1320 uint64_t tick_jump_limit; 1321 uint64_t mondo_time_limit; 1322 uint64_t func_time_limit; 1323 uint64_t scale; 1324 1325 uint64_t latency; /* nanoseconds */ 1326 uint64_t maxfreq; 1327 uint64_t tick_limit_save = xc_tick_limit; 1328 uint_t tick_scale; 1329 uint64_t top; 1330 uint64_t bottom; 1331 u_number tk; 1332 1333 md_t *mdp; 1334 int nrnode; 1335 mde_cookie_t *platlist; 1336 1337 /* 1338 * Look up the 'inter-cpu-latency' (optional) property in the 1339 * platform node of the MD. The units are nanoseconds. 1340 */ 1341 if ((mdp = md_get_handle()) == NULL) { 1342 cmn_err(CE_WARN, "recalc_xc_timeouts: " 1343 "Unable to initialize machine description"); 1344 return; 1345 } 1346 1347 nrnode = md_alloc_scan_dag(mdp, 1348 md_root_node(mdp), "platform", "fwd", &platlist); 1349 1350 ASSERT(nrnode == 1); 1351 if (nrnode < 1) { 1352 cmn_err(CE_WARN, "recalc_xc_timeouts: platform node missing"); 1353 goto done; 1354 } 1355 1356 if (md_get_prop_val(mdp, platlist[0], 1357 "inter-cpu-latency", &latency) == -1) 1358 goto done; 1359 1360 /* 1361 * clock.h defines an assembly-language macro 1362 * (NATIVE_TIME_TO_NSEC_SCALE) to convert from %stick 1363 * units to nanoseconds. Since the inter-cpu-latency 1364 * units are nanoseconds and the xc_* variables require 1365 * %stick units, we need the inverse of that function. 1366 * The trick is to perform the calculation without 1367 * floating point, but also without integer truncation 1368 * or overflow. To understand the calculation below, 1369 * please read the discussion of the macro in clock.h. 1370 * Since this new code will be invoked infrequently, 1371 * we can afford to implement it in C. 1372 * 1373 * tick_scale is the reciprocal of nsec_scale which is 1374 * calculated at startup in setcpudelay(). The calc 1375 * of tick_limit parallels that of NATIVE_TIME_TO_NSEC_SCALE 1376 * except we use tick_scale instead of nsec_scale and 1377 * C instead of assembler. 1378 */ 1379 tick_scale = (uint_t)(((u_longlong_t)sys_tick_freq 1380 << (32 - nsec_shift)) / NANOSEC); 1381 1382 tk.whole = latency; 1383 top = ((uint64_t)tk.half.high << 4) * tick_scale; 1384 bottom = (((uint64_t)tk.half.low << 4) * (uint64_t)tick_scale) >> 32; 1385 tick_limit = top + bottom; 1386 1387 1388 /* 1389 * xc_init() calculated 'maxfreq' by looking at all the cpus, 1390 * and used it to derive some of the timeout variables that we 1391 * recalculate below. We can back into the original value by 1392 * using the inverse of one of those calculations. 1393 */ 1394 maxfreq = xc_mondo_time_limit / xc_scale; 1395 1396 /* 1397 * Don't allow the new timeout (xc_tick_limit) to fall below 1398 * the system tick frequency (stick). Allowing the timeout 1399 * to be set more tightly than this empirically determined 1400 * value may cause panics. 1401 */ 1402 tick_limit = tick_limit < sys_tick_freq ? sys_tick_freq : tick_limit; 1403 1404 tick_jump_limit = tick_limit / 32; 1405 tick_limit *= xc_tick_limit_scale; 1406 1407 /* 1408 * Recalculate xc_scale since it is used in a callback function 1409 * (xc_func_timeout_adj) to adjust two of the timeouts dynamically. 1410 * Make the change in xc_scale proportional to the change in 1411 * xc_tick_limit. 1412 */ 1413 scale = (xc_scale * tick_limit + sys_tick_freq / 2) / tick_limit_save; 1414 if (scale == 0) 1415 scale = 1; 1416 1417 mondo_time_limit = maxfreq * scale; 1418 func_time_limit = mondo_time_limit * xc_mondo_multiplier; 1419 1420 /* 1421 * Don't modify the timeouts if nothing has changed. Else, 1422 * stuff the variables with the freshly calculated (temp) 1423 * variables. This minimizes the window where the set of 1424 * values could be inconsistent. 1425 */ 1426 if (tick_limit != xc_tick_limit) { 1427 xc_tick_limit = tick_limit; 1428 xc_tick_jump_limit = tick_jump_limit; 1429 xc_scale = scale; 1430 xc_mondo_time_limit = mondo_time_limit; 1431 xc_func_time_limit = func_time_limit; 1432 /* 1433 * Force the new values to be used for future cross 1434 * calls. This is necessary only when we increase 1435 * the timeouts. 1436 */ 1437 if (tick_limit > tick_limit_save) { 1438 cpuset_t cpuset = cpu_ready_set; 1439 1440 xt_sync(cpuset); 1441 } 1442 } 1443 1444 done: 1445 if (nrnode > 0) 1446 md_free_scan_dag(mdp, &platlist); 1447 (void) md_fini_handle(mdp); 1448 } 1449 1450 void 1451 mach_soft_state_init(void) 1452 { 1453 int i; 1454 uint64_t ra; 1455 1456 /* 1457 * Try to register soft_state api. If it fails, soft_state api has not 1458 * been implemented in the firmware, so do not bother to setup 1459 * soft_state in the kernel. 1460 */ 1461 if ((i = hsvc_register(&soft_state_hsvc, &soft_state_sup_minor)) != 0) { 1462 return; 1463 } 1464 for (i = 0; i < SOLARIS_SOFT_STATE_MSG_CNT; i++) { 1465 ASSERT(strlen((const char *)(void *) 1466 soft_state_message_strings + i) < SSM_SIZE); 1467 if ((ra = va_to_pa( 1468 (void *)(soft_state_message_strings + i))) == -1ll) { 1469 return; 1470 } 1471 soft_state_message_ra[i] = ra; 1472 } 1473 /* 1474 * Tell OBP that we are supporting Guest State 1475 */ 1476 prom_sun4v_soft_state_supported(); 1477 soft_state_initialized = 1; 1478 } 1479 1480 void 1481 mach_set_soft_state(uint64_t state, uint64_t *string_ra) 1482 { 1483 uint64_t rc; 1484 1485 if (soft_state_initialized && *string_ra) { 1486 rc = hv_soft_state_set(state, *string_ra); 1487 if (rc != H_EOK) { 1488 cmn_err(CE_WARN, 1489 "hv_soft_state_set returned %ld\n", rc); 1490 } 1491 } 1492 } 1493 1494 void 1495 mach_get_soft_state(uint64_t *state, uint64_t *string_ra) 1496 { 1497 uint64_t rc; 1498 1499 if (soft_state_initialized && *string_ra) { 1500 rc = hv_soft_state_get(*string_ra, state); 1501 if (rc != H_EOK) { 1502 cmn_err(CE_WARN, 1503 "hv_soft_state_get returned %ld\n", rc); 1504 *state = -1; 1505 } 1506 } 1507 } 1508