17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 51ce12b49Svb70745 * Common Development and Distribution License (the "License"). 61ce12b49Svb70745 * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 221ce12b49Svb70745 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate #include <sys/types.h> 297c478bd9Sstevel@tonic-gate #include <vm/hat.h> 307c478bd9Sstevel@tonic-gate #include <vm/hat_sfmmu.h> 317c478bd9Sstevel@tonic-gate #include <vm/page.h> 327c478bd9Sstevel@tonic-gate #include <sys/pte.h> 337c478bd9Sstevel@tonic-gate #include <sys/systm.h> 347c478bd9Sstevel@tonic-gate #include <sys/mman.h> 357c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 367c478bd9Sstevel@tonic-gate #include <sys/machparam.h> 377c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 387c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 397c478bd9Sstevel@tonic-gate #include <sys/mmu.h> 407c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 417c478bd9Sstevel@tonic-gate #include <sys/cpu.h> 427c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 437c478bd9Sstevel@tonic-gate #include <sys/debug.h> 447c478bd9Sstevel@tonic-gate #include <sys/lgrp.h> 457c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 467c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 477c478bd9Sstevel@tonic-gate #include <sys/vmsystm.h> 487c478bd9Sstevel@tonic-gate #include <sys/bitmap.h> 497c478bd9Sstevel@tonic-gate #include <vm/rm.h> 507c478bd9Sstevel@tonic-gate #include <sys/t_lock.h> 517c478bd9Sstevel@tonic-gate #include <sys/vm_machparam.h> 527c478bd9Sstevel@tonic-gate #include <sys/promif.h> 537c478bd9Sstevel@tonic-gate #include <sys/prom_isa.h> 547c478bd9Sstevel@tonic-gate #include <sys/prom_plat.h> 557c478bd9Sstevel@tonic-gate #include <sys/prom_debug.h> 567c478bd9Sstevel@tonic-gate #include <sys/privregs.h> 577c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 587c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 597c478bd9Sstevel@tonic-gate #include <sys/memlist_plat.h> 607c478bd9Sstevel@tonic-gate #include <sys/cpu_module.h> 617c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 627c478bd9Sstevel@tonic-gate #include <sys/kdi.h> 637c478bd9Sstevel@tonic-gate #include <sys/hypervisor_api.h> 647c478bd9Sstevel@tonic-gate 657c478bd9Sstevel@tonic-gate /* 667c478bd9Sstevel@tonic-gate * External routines and data structures 677c478bd9Sstevel@tonic-gate */ 687c478bd9Sstevel@tonic-gate extern void sfmmu_cache_flushcolor(int, pfn_t); 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate /* 717c478bd9Sstevel@tonic-gate * Static routines 727c478bd9Sstevel@tonic-gate */ 737c478bd9Sstevel@tonic-gate static void sfmmu_set_tlb(void); 747c478bd9Sstevel@tonic-gate 757c478bd9Sstevel@tonic-gate /* 767c478bd9Sstevel@tonic-gate * Global Data: 777c478bd9Sstevel@tonic-gate */ 787c478bd9Sstevel@tonic-gate caddr_t textva, datava; 797c478bd9Sstevel@tonic-gate tte_t ktext_tte, kdata_tte; /* ttes for kernel text and data */ 807c478bd9Sstevel@tonic-gate 817c478bd9Sstevel@tonic-gate int enable_bigktsb = 1; 827c478bd9Sstevel@tonic-gate 837c478bd9Sstevel@tonic-gate tte_t bigktsb_ttes[MAX_BIGKTSB_TTES]; 847c478bd9Sstevel@tonic-gate int bigktsb_nttes = 0; 857c478bd9Sstevel@tonic-gate 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate /* 887c478bd9Sstevel@tonic-gate * Controls the logic which enables the use of the 897c478bd9Sstevel@tonic-gate * QUAD_LDD_PHYS ASI for TSB accesses. 907c478bd9Sstevel@tonic-gate */ 917c478bd9Sstevel@tonic-gate int ktsb_phys = 1; 927c478bd9Sstevel@tonic-gate 937c478bd9Sstevel@tonic-gate #ifdef SET_MMU_STATS 947c478bd9Sstevel@tonic-gate struct mmu_stat mmu_stat_area[NCPU]; 957c478bd9Sstevel@tonic-gate #endif /* SET_MMU_STATS */ 967c478bd9Sstevel@tonic-gate 977c478bd9Sstevel@tonic-gate #ifdef DEBUG 987c478bd9Sstevel@tonic-gate /* 997c478bd9Sstevel@tonic-gate * The following two variables control if the hypervisor/hardware will 1007c478bd9Sstevel@tonic-gate * be used to do the TSB table walk for kernel and user contexts. 1017c478bd9Sstevel@tonic-gate */ 1027c478bd9Sstevel@tonic-gate int hv_use_0_tsb = 1; 1037c478bd9Sstevel@tonic-gate int hv_use_non0_tsb = 1; 1047c478bd9Sstevel@tonic-gate #endif /* DEBUG */ 1057c478bd9Sstevel@tonic-gate 1067c478bd9Sstevel@tonic-gate static void 1077c478bd9Sstevel@tonic-gate sfmmu_set_fault_status_area(void) 1087c478bd9Sstevel@tonic-gate { 1097c478bd9Sstevel@tonic-gate caddr_t mmfsa_va; 1107c478bd9Sstevel@tonic-gate extern caddr_t mmu_fault_status_area; 1117c478bd9Sstevel@tonic-gate 1127c478bd9Sstevel@tonic-gate mmfsa_va = 1137c478bd9Sstevel@tonic-gate mmu_fault_status_area + (MMFSA_SIZE * getprocessorid()); 1147c478bd9Sstevel@tonic-gate set_mmfsa_scratchpad(mmfsa_va); 1157c478bd9Sstevel@tonic-gate prom_set_mmfsa_traptable(&trap_table, va_to_pa(mmfsa_va)); 1167c478bd9Sstevel@tonic-gate } 1177c478bd9Sstevel@tonic-gate 1187c478bd9Sstevel@tonic-gate void 1197c478bd9Sstevel@tonic-gate sfmmu_set_tsbs() 1207c478bd9Sstevel@tonic-gate { 1217c478bd9Sstevel@tonic-gate uint64_t rv; 1227c478bd9Sstevel@tonic-gate struct hv_tsb_block *hvbp = &ksfmmup->sfmmu_hvblock; 1237c478bd9Sstevel@tonic-gate 1247c478bd9Sstevel@tonic-gate #ifdef DEBUG 1257c478bd9Sstevel@tonic-gate if (hv_use_0_tsb == 0) 1267c478bd9Sstevel@tonic-gate return; 1277c478bd9Sstevel@tonic-gate #endif /* DEBUG */ 1287c478bd9Sstevel@tonic-gate 1297c478bd9Sstevel@tonic-gate rv = hv_set_ctx0(hvbp->hv_tsb_info_cnt, 1307c478bd9Sstevel@tonic-gate hvbp->hv_tsb_info_pa); 1317c478bd9Sstevel@tonic-gate if (rv != H_EOK) 1327c478bd9Sstevel@tonic-gate prom_printf("cpu%d: hv_set_ctx0() returned %lx\n", 1337c478bd9Sstevel@tonic-gate getprocessorid(), rv); 1347c478bd9Sstevel@tonic-gate 1357c478bd9Sstevel@tonic-gate #ifdef SET_MMU_STATS 1367c478bd9Sstevel@tonic-gate ASSERT(getprocessorid() < NCPU); 1377c478bd9Sstevel@tonic-gate rv = hv_mmu_set_stat_area(va_to_pa(&mmu_stat_area[getprocessorid()]), 1387c478bd9Sstevel@tonic-gate sizeof (mmu_stat_area[0])); 1397c478bd9Sstevel@tonic-gate if (rv != H_EOK) 1407c478bd9Sstevel@tonic-gate prom_printf("cpu%d: hv_mmu_set_stat_area() returned %lx\n", 1417c478bd9Sstevel@tonic-gate getprocessorid(), rv); 1427c478bd9Sstevel@tonic-gate #endif /* SET_MMU_STATS */ 1437c478bd9Sstevel@tonic-gate } 1447c478bd9Sstevel@tonic-gate 1457c478bd9Sstevel@tonic-gate /* 1467c478bd9Sstevel@tonic-gate * This routine remaps the kernel using large ttes 1477c478bd9Sstevel@tonic-gate * All entries except locked ones will be removed from the tlb. 1487c478bd9Sstevel@tonic-gate * It assumes that both the text and data segments reside in a separate 1497c478bd9Sstevel@tonic-gate * 4mb virtual and physical contigous memory chunk. This routine 1507c478bd9Sstevel@tonic-gate * is only executed by the first cpu. The remaining cpus execute 1517c478bd9Sstevel@tonic-gate * sfmmu_mp_startup() instead. 1527c478bd9Sstevel@tonic-gate * XXX It assumes that the start of the text segment is KERNELBASE. It should 1537c478bd9Sstevel@tonic-gate * actually be based on start. 1547c478bd9Sstevel@tonic-gate */ 1557c478bd9Sstevel@tonic-gate void 1567c478bd9Sstevel@tonic-gate sfmmu_remap_kernel(void) 1577c478bd9Sstevel@tonic-gate { 1587c478bd9Sstevel@tonic-gate pfn_t pfn; 1597c478bd9Sstevel@tonic-gate uint_t attr; 1607c478bd9Sstevel@tonic-gate int flags; 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate extern char end[]; 1637c478bd9Sstevel@tonic-gate extern struct as kas; 1647c478bd9Sstevel@tonic-gate 1657c478bd9Sstevel@tonic-gate textva = (caddr_t)(KERNELBASE & MMU_PAGEMASK4M); 1667c478bd9Sstevel@tonic-gate pfn = va_to_pfn(textva); 1677c478bd9Sstevel@tonic-gate if (pfn == PFN_INVALID) 1687c478bd9Sstevel@tonic-gate prom_panic("can't find kernel text pfn"); 1697c478bd9Sstevel@tonic-gate pfn &= TTE_PFNMASK(TTE4M); 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate attr = PROC_TEXT | HAT_NOSYNC; 1727c478bd9Sstevel@tonic-gate flags = HAT_LOAD_LOCK | SFMMU_NO_TSBLOAD; 1737c478bd9Sstevel@tonic-gate sfmmu_memtte(&ktext_tte, pfn, attr, TTE4M); 1747c478bd9Sstevel@tonic-gate /* 1757c478bd9Sstevel@tonic-gate * We set the lock bit in the tte to lock the translation in 1767c478bd9Sstevel@tonic-gate * the tlb. 1777c478bd9Sstevel@tonic-gate */ 1787c478bd9Sstevel@tonic-gate TTE_SET_LOCKED(&ktext_tte); 1797c478bd9Sstevel@tonic-gate sfmmu_tteload(kas.a_hat, &ktext_tte, textva, NULL, flags); 1807c478bd9Sstevel@tonic-gate 1817c478bd9Sstevel@tonic-gate datava = (caddr_t)((uintptr_t)end & MMU_PAGEMASK4M); 1827c478bd9Sstevel@tonic-gate pfn = va_to_pfn(datava); 1837c478bd9Sstevel@tonic-gate if (pfn == PFN_INVALID) 1847c478bd9Sstevel@tonic-gate prom_panic("can't find kernel data pfn"); 1857c478bd9Sstevel@tonic-gate pfn &= TTE_PFNMASK(TTE4M); 1867c478bd9Sstevel@tonic-gate 1877c478bd9Sstevel@tonic-gate attr = PROC_DATA | HAT_NOSYNC; 1887c478bd9Sstevel@tonic-gate sfmmu_memtte(&kdata_tte, pfn, attr, TTE4M); 1897c478bd9Sstevel@tonic-gate /* 1907c478bd9Sstevel@tonic-gate * We set the lock bit in the tte to lock the translation in 1917c478bd9Sstevel@tonic-gate * the tlb. We also set the mod bit to avoid taking dirty bit 1927c478bd9Sstevel@tonic-gate * traps on kernel data. 1937c478bd9Sstevel@tonic-gate */ 1947c478bd9Sstevel@tonic-gate TTE_SET_LOCKED(&kdata_tte); 1957c478bd9Sstevel@tonic-gate TTE_SET_LOFLAGS(&kdata_tte, 0, TTE_HWWR_INT); 1967c478bd9Sstevel@tonic-gate sfmmu_tteload(kas.a_hat, &kdata_tte, datava, 1977c478bd9Sstevel@tonic-gate (struct page *)NULL, flags); 1987c478bd9Sstevel@tonic-gate 1997c478bd9Sstevel@tonic-gate /* 2007c478bd9Sstevel@tonic-gate * create bigktsb ttes if necessary. 2017c478bd9Sstevel@tonic-gate */ 2027c478bd9Sstevel@tonic-gate if (enable_bigktsb) { 2037c478bd9Sstevel@tonic-gate int i = 0; 2047c478bd9Sstevel@tonic-gate caddr_t va = ktsb_base; 2057c478bd9Sstevel@tonic-gate size_t tsbsz = ktsb_sz; 2067c478bd9Sstevel@tonic-gate tte_t tte; 2077c478bd9Sstevel@tonic-gate 2087c478bd9Sstevel@tonic-gate ASSERT(va >= datava + MMU_PAGESIZE4M); 2097c478bd9Sstevel@tonic-gate ASSERT(tsbsz >= MMU_PAGESIZE4M); 2107c478bd9Sstevel@tonic-gate ASSERT(IS_P2ALIGNED(tsbsz, tsbsz)); 2117c478bd9Sstevel@tonic-gate ASSERT(IS_P2ALIGNED(va, tsbsz)); 2127c478bd9Sstevel@tonic-gate attr = PROC_DATA | HAT_NOSYNC; 2137c478bd9Sstevel@tonic-gate while (tsbsz != 0) { 2147c478bd9Sstevel@tonic-gate ASSERT(i < MAX_BIGKTSB_TTES); 2157c478bd9Sstevel@tonic-gate pfn = va_to_pfn(va); 2167c478bd9Sstevel@tonic-gate ASSERT(pfn != PFN_INVALID); 2177c478bd9Sstevel@tonic-gate ASSERT((pfn & ~TTE_PFNMASK(TTE4M)) == 0); 2187c478bd9Sstevel@tonic-gate sfmmu_memtte(&tte, pfn, attr, TTE4M); 2197c478bd9Sstevel@tonic-gate ASSERT(TTE_IS_MOD(&tte)); 2207c478bd9Sstevel@tonic-gate /* 2217c478bd9Sstevel@tonic-gate * No need to lock if we use physical addresses. 2227c478bd9Sstevel@tonic-gate * Since we invalidate the kernel TSB using virtual 2237c478bd9Sstevel@tonic-gate * addresses, it's an optimization to load them now 2247c478bd9Sstevel@tonic-gate * so that we won't have to load them later. 2257c478bd9Sstevel@tonic-gate */ 2267c478bd9Sstevel@tonic-gate if (!ktsb_phys) { 2277c478bd9Sstevel@tonic-gate TTE_SET_LOCKED(&tte); 2287c478bd9Sstevel@tonic-gate } 2297c478bd9Sstevel@tonic-gate sfmmu_tteload(kas.a_hat, &tte, va, NULL, flags); 2307c478bd9Sstevel@tonic-gate bigktsb_ttes[i] = tte; 2317c478bd9Sstevel@tonic-gate va += MMU_PAGESIZE4M; 2327c478bd9Sstevel@tonic-gate tsbsz -= MMU_PAGESIZE4M; 2337c478bd9Sstevel@tonic-gate i++; 2347c478bd9Sstevel@tonic-gate } 2357c478bd9Sstevel@tonic-gate bigktsb_nttes = i; 2367c478bd9Sstevel@tonic-gate } 2377c478bd9Sstevel@tonic-gate 2387c478bd9Sstevel@tonic-gate sfmmu_set_tlb(); 2397c478bd9Sstevel@tonic-gate } 2407c478bd9Sstevel@tonic-gate 2417c478bd9Sstevel@tonic-gate /* 2427c478bd9Sstevel@tonic-gate * Setup the kernel's locked tte's 2437c478bd9Sstevel@tonic-gate */ 2447c478bd9Sstevel@tonic-gate void 2457c478bd9Sstevel@tonic-gate sfmmu_set_tlb(void) 2467c478bd9Sstevel@tonic-gate { 2477c478bd9Sstevel@tonic-gate (void) hv_mmu_map_perm_addr(textva, KCONTEXT, *(uint64_t *)&ktext_tte, 2487c478bd9Sstevel@tonic-gate MAP_ITLB | MAP_DTLB); 2497c478bd9Sstevel@tonic-gate (void) hv_mmu_map_perm_addr(datava, KCONTEXT, *(uint64_t *)&kdata_tte, 2507c478bd9Sstevel@tonic-gate MAP_DTLB); 2517c478bd9Sstevel@tonic-gate 2527c478bd9Sstevel@tonic-gate if (!ktsb_phys && enable_bigktsb) { 2537c478bd9Sstevel@tonic-gate int i; 2547c478bd9Sstevel@tonic-gate caddr_t va = ktsb_base; 2557c478bd9Sstevel@tonic-gate uint64_t tte; 2567c478bd9Sstevel@tonic-gate 2577c478bd9Sstevel@tonic-gate ASSERT(bigktsb_nttes <= MAX_BIGKTSB_TTES); 2587c478bd9Sstevel@tonic-gate for (i = 0; i < bigktsb_nttes; i++) { 2597c478bd9Sstevel@tonic-gate tte = *(uint64_t *)&bigktsb_ttes[i]; 2607c478bd9Sstevel@tonic-gate (void) hv_mmu_map_perm_addr(va, KCONTEXT, tte, 2617c478bd9Sstevel@tonic-gate MAP_DTLB); 2627c478bd9Sstevel@tonic-gate va += MMU_PAGESIZE4M; 2637c478bd9Sstevel@tonic-gate } 2647c478bd9Sstevel@tonic-gate } 2657c478bd9Sstevel@tonic-gate } 2667c478bd9Sstevel@tonic-gate 2677c478bd9Sstevel@tonic-gate /* 2687c478bd9Sstevel@tonic-gate * This routine is executed by all other cpus except the first one 2697c478bd9Sstevel@tonic-gate * at initialization time. It is responsible for taking over the 2707c478bd9Sstevel@tonic-gate * mmu from the prom. We follow these steps. 2717c478bd9Sstevel@tonic-gate * Lock the kernel's ttes in the TLB 2727c478bd9Sstevel@tonic-gate * Initialize the tsb hardware registers 2737c478bd9Sstevel@tonic-gate * Take over the trap table 2747c478bd9Sstevel@tonic-gate * Flush the prom's locked entries from the TLB 2757c478bd9Sstevel@tonic-gate */ 2767c478bd9Sstevel@tonic-gate void 2777c478bd9Sstevel@tonic-gate sfmmu_mp_startup(void) 2787c478bd9Sstevel@tonic-gate { 2797c478bd9Sstevel@tonic-gate sfmmu_set_tlb(); 2807c478bd9Sstevel@tonic-gate setwstate(WSTATE_KERN); 2817c478bd9Sstevel@tonic-gate /* 2827c478bd9Sstevel@tonic-gate * sfmmu_set_fault_status_area() takes over trap_table 2837c478bd9Sstevel@tonic-gate */ 2847c478bd9Sstevel@tonic-gate sfmmu_set_fault_status_area(); 2857c478bd9Sstevel@tonic-gate sfmmu_set_tsbs(); 2867c478bd9Sstevel@tonic-gate install_va_to_tte(); 2877c478bd9Sstevel@tonic-gate } 2887c478bd9Sstevel@tonic-gate 2897c478bd9Sstevel@tonic-gate void 2907c478bd9Sstevel@tonic-gate kdi_tlb_page_lock(caddr_t va, int do_dtlb) 2917c478bd9Sstevel@tonic-gate { 2927c478bd9Sstevel@tonic-gate tte_t tte; 2937c478bd9Sstevel@tonic-gate pfn_t pfn = va_to_pfn(va); 2947c478bd9Sstevel@tonic-gate uint64_t ret; 2957c478bd9Sstevel@tonic-gate 2967c478bd9Sstevel@tonic-gate sfmmu_memtte(&tte, pfn, (PROC_TEXT | HAT_NOSYNC), TTE8K); 2977c478bd9Sstevel@tonic-gate ret = hv_mmu_map_perm_addr(va, KCONTEXT, *(uint64_t *)&tte, 2987c478bd9Sstevel@tonic-gate MAP_ITLB | (do_dtlb ? MAP_DTLB : 0)); 2997c478bd9Sstevel@tonic-gate 3007c478bd9Sstevel@tonic-gate if (ret != H_EOK) { 3017c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "cpu%d: cannot set permanent mapping for " 302*44961713Sgirish "va=0x%p, hv error code 0x%lx", 3037c478bd9Sstevel@tonic-gate getprocessorid(), (void *)va, ret); 3047c478bd9Sstevel@tonic-gate } 3057c478bd9Sstevel@tonic-gate } 3067c478bd9Sstevel@tonic-gate 3077c478bd9Sstevel@tonic-gate void 3087c478bd9Sstevel@tonic-gate kdi_tlb_page_unlock(caddr_t va, int do_dtlb) 3097c478bd9Sstevel@tonic-gate { 3107c478bd9Sstevel@tonic-gate (void) hv_mmu_unmap_perm_addr(va, KCONTEXT, 3117c478bd9Sstevel@tonic-gate MAP_ITLB | (do_dtlb ? MAP_DTLB : 0)); 3127c478bd9Sstevel@tonic-gate } 3137c478bd9Sstevel@tonic-gate 3147c478bd9Sstevel@tonic-gate /* 3157c478bd9Sstevel@tonic-gate * Clear machine specific TSB information for a user process 3167c478bd9Sstevel@tonic-gate */ 3177c478bd9Sstevel@tonic-gate void 3187c478bd9Sstevel@tonic-gate sfmmu_clear_utsbinfo() 3197c478bd9Sstevel@tonic-gate { 3207c478bd9Sstevel@tonic-gate (void) hv_set_ctxnon0(0, NULL); 3217c478bd9Sstevel@tonic-gate } 3227c478bd9Sstevel@tonic-gate 3237c478bd9Sstevel@tonic-gate /* 3241ce12b49Svb70745 * Invalidate machine specific TSB information, indicates all TSB memory 3251ce12b49Svb70745 * is being freed by hat_swapout(). 3261ce12b49Svb70745 */ 3271ce12b49Svb70745 void 3281ce12b49Svb70745 sfmmu_invalidate_tsbinfo(sfmmu_t *sfmmup) 3291ce12b49Svb70745 { 3301ce12b49Svb70745 ASSERT(sfmmup->sfmmu_tsb != NULL && 3311ce12b49Svb70745 sfmmup->sfmmu_tsb->tsb_flags & TSB_SWAPPED); 3321ce12b49Svb70745 3331ce12b49Svb70745 sfmmup->sfmmu_hvblock.hv_tsb_info_pa = (uint64_t)-1; 3341ce12b49Svb70745 sfmmup->sfmmu_hvblock.hv_tsb_info_cnt = 0; 3351ce12b49Svb70745 } 3361ce12b49Svb70745 3371ce12b49Svb70745 /* 3387c478bd9Sstevel@tonic-gate * Set machine specific TSB information 3397c478bd9Sstevel@tonic-gate */ 3407c478bd9Sstevel@tonic-gate void 3417c478bd9Sstevel@tonic-gate sfmmu_setup_tsbinfo(sfmmu_t *sfmmup) 3427c478bd9Sstevel@tonic-gate { 3437c478bd9Sstevel@tonic-gate struct tsb_info *tsbinfop; 3447c478bd9Sstevel@tonic-gate hv_tsb_info_t *tdp; 3457c478bd9Sstevel@tonic-gate 3467c478bd9Sstevel@tonic-gate tsbinfop = sfmmup->sfmmu_tsb; 3477c478bd9Sstevel@tonic-gate if (tsbinfop == NULL) { 3487c478bd9Sstevel@tonic-gate sfmmup->sfmmu_hvblock.hv_tsb_info_pa = (uint64_t)-1; 3497c478bd9Sstevel@tonic-gate sfmmup->sfmmu_hvblock.hv_tsb_info_cnt = 0; 3507c478bd9Sstevel@tonic-gate return; 3517c478bd9Sstevel@tonic-gate } 3527c478bd9Sstevel@tonic-gate tdp = &sfmmup->sfmmu_hvblock.hv_tsb_info[0]; 3537c478bd9Sstevel@tonic-gate sfmmup->sfmmu_hvblock.hv_tsb_info_pa = va_to_pa(tdp); 3547c478bd9Sstevel@tonic-gate sfmmup->sfmmu_hvblock.hv_tsb_info_cnt = 1; 3557c478bd9Sstevel@tonic-gate tdp->hvtsb_idxpgsz = TTE8K; 3567c478bd9Sstevel@tonic-gate tdp->hvtsb_assoc = 1; 3577c478bd9Sstevel@tonic-gate tdp->hvtsb_ntte = TSB_ENTRIES(tsbinfop->tsb_szc); 3587c478bd9Sstevel@tonic-gate tdp->hvtsb_ctx_index = 0; 3597c478bd9Sstevel@tonic-gate tdp->hvtsb_pgszs = tsbinfop->tsb_ttesz_mask; 3607c478bd9Sstevel@tonic-gate tdp->hvtsb_rsvd = 0; 3617c478bd9Sstevel@tonic-gate tdp->hvtsb_pa = tsbinfop->tsb_pa; 3627c478bd9Sstevel@tonic-gate if ((tsbinfop = tsbinfop->tsb_next) == NULL) 3637c478bd9Sstevel@tonic-gate return; 3647c478bd9Sstevel@tonic-gate sfmmup->sfmmu_hvblock.hv_tsb_info_cnt++; 3657c478bd9Sstevel@tonic-gate tdp++; 3667c478bd9Sstevel@tonic-gate tdp->hvtsb_idxpgsz = TTE4M; 3677c478bd9Sstevel@tonic-gate tdp->hvtsb_assoc = 1; 3687c478bd9Sstevel@tonic-gate tdp->hvtsb_ntte = TSB_ENTRIES(tsbinfop->tsb_szc); 3697c478bd9Sstevel@tonic-gate tdp->hvtsb_ctx_index = 0; 3707c478bd9Sstevel@tonic-gate tdp->hvtsb_pgszs = tsbinfop->tsb_ttesz_mask; 3717c478bd9Sstevel@tonic-gate tdp->hvtsb_rsvd = 0; 3727c478bd9Sstevel@tonic-gate tdp->hvtsb_pa = tsbinfop->tsb_pa; 3737c478bd9Sstevel@tonic-gate /* Only allow for 2 TSBs */ 3747c478bd9Sstevel@tonic-gate ASSERT(tsbinfop->tsb_next == NULL); 3757c478bd9Sstevel@tonic-gate } 3767c478bd9Sstevel@tonic-gate 3777c478bd9Sstevel@tonic-gate /* 3787c478bd9Sstevel@tonic-gate * Invalidate a TSB via processor specific TSB invalidation routine 3797c478bd9Sstevel@tonic-gate */ 3807c478bd9Sstevel@tonic-gate void 3817c478bd9Sstevel@tonic-gate sfmmu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes) 3827c478bd9Sstevel@tonic-gate { 3837c478bd9Sstevel@tonic-gate extern void cpu_inv_tsb(caddr_t, uint_t); 3847c478bd9Sstevel@tonic-gate 3857c478bd9Sstevel@tonic-gate cpu_inv_tsb(tsb_base, tsb_bytes); 3867c478bd9Sstevel@tonic-gate } 3877c478bd9Sstevel@tonic-gate 3887c478bd9Sstevel@tonic-gate /* 3897c478bd9Sstevel@tonic-gate * Completely flush the D-cache on all cpus. 3907c478bd9Sstevel@tonic-gate * Not applicable to sun4v. 3917c478bd9Sstevel@tonic-gate */ 3927c478bd9Sstevel@tonic-gate void 3937c478bd9Sstevel@tonic-gate sfmmu_cache_flushall() 3947c478bd9Sstevel@tonic-gate { 3957c478bd9Sstevel@tonic-gate } 396