1*92b3de3fSJonathan Corbet================= 2*92b3de3fSJonathan CorbetPA-RISC Debugging 3*92b3de3fSJonathan Corbet================= 4*92b3de3fSJonathan Corbet 5*92b3de3fSJonathan Corbetokay, here are some hints for debugging the lower-level parts of 6*92b3de3fSJonathan Corbetlinux/parisc. 7*92b3de3fSJonathan Corbet 8*92b3de3fSJonathan Corbet 9*92b3de3fSJonathan Corbet1. Absolute addresses 10*92b3de3fSJonathan Corbet===================== 11*92b3de3fSJonathan Corbet 12*92b3de3fSJonathan CorbetA lot of the assembly code currently runs in real mode, which means 13*92b3de3fSJonathan Corbetabsolute addresses are used instead of virtual addresses as in the 14*92b3de3fSJonathan Corbetrest of the kernel. To translate an absolute address to a virtual 15*92b3de3fSJonathan Corbetaddress you can lookup in System.map, add __PAGE_OFFSET (0x10000000 16*92b3de3fSJonathan Corbetcurrently). 17*92b3de3fSJonathan Corbet 18*92b3de3fSJonathan Corbet 19*92b3de3fSJonathan Corbet2. HPMCs 20*92b3de3fSJonathan Corbet======== 21*92b3de3fSJonathan Corbet 22*92b3de3fSJonathan CorbetWhen real-mode code tries to access non-existent memory, you'll get 23*92b3de3fSJonathan Corbetan HPMC instead of a kernel oops. To debug an HPMC, try to find 24*92b3de3fSJonathan Corbetthe System Responder/Requestor addresses. The System Requestor 25*92b3de3fSJonathan Corbetaddress should match (one of the) processor HPAs (high addresses in 26*92b3de3fSJonathan Corbetthe I/O range); the System Responder address is the address real-mode 27*92b3de3fSJonathan Corbetcode tried to access. 28*92b3de3fSJonathan Corbet 29*92b3de3fSJonathan CorbetTypical values for the System Responder address are addresses larger 30*92b3de3fSJonathan Corbetthan __PAGE_OFFSET (0x10000000) which mean a virtual address didn't 31*92b3de3fSJonathan Corbetget translated to a physical address before real-mode code tried to 32*92b3de3fSJonathan Corbetaccess it. 33*92b3de3fSJonathan Corbet 34*92b3de3fSJonathan Corbet 35*92b3de3fSJonathan Corbet3. Q bit fun 36*92b3de3fSJonathan Corbet============ 37*92b3de3fSJonathan Corbet 38*92b3de3fSJonathan CorbetCertain, very critical code has to clear the Q bit in the PSW. What 39*92b3de3fSJonathan Corbethappens when the Q bit is cleared is the CPU does not update the 40*92b3de3fSJonathan Corbetregisters interruption handlers read to find out where the machine 41*92b3de3fSJonathan Corbetwas interrupted - so if you get an interruption between the instruction 42*92b3de3fSJonathan Corbetthat clears the Q bit and the RFI that sets it again you don't know 43*92b3de3fSJonathan Corbetwhere exactly it happened. If you're lucky the IAOQ will point to the 44*92b3de3fSJonathan Corbetinstruction that cleared the Q bit, if you're not it points anywhere 45*92b3de3fSJonathan Corbetat all. Usually Q bit problems will show themselves in unexplainable 46*92b3de3fSJonathan Corbetsystem hangs or running off the end of physical memory. 47