13c15fddfSRob Herring# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 23c15fddfSRob Herring%YAML 1.2 33c15fddfSRob Herring--- 43c15fddfSRob Herring$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml# 53c15fddfSRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 63c15fddfSRob Herring 73c15fddfSRob Herringtitle: Arm Coresight Address Translation Unit (CATU) 83c15fddfSRob Herring 93c15fddfSRob Herringmaintainers: 103c15fddfSRob Herring - Mathieu Poirier <mathieu.poirier@linaro.org> 113c15fddfSRob Herring - Mike Leach <mike.leach@linaro.org> 123c15fddfSRob Herring - Leo Yan <leo.yan@linaro.org> 133c15fddfSRob Herring - Suzuki K Poulose <suzuki.poulose@arm.com> 143c15fddfSRob Herring 153c15fddfSRob Herringdescription: | 163c15fddfSRob Herring CoreSight components are compliant with the ARM CoreSight architecture 173c15fddfSRob Herring specification and can be connected in various topologies to suit a particular 183c15fddfSRob Herring SoCs tracing needs. These trace components can generally be classified as 193c15fddfSRob Herring sinks, links and sources. Trace data produced by one or more sources flows 203c15fddfSRob Herring through the intermediate links connecting the source to the currently selected 213c15fddfSRob Herring sink. 223c15fddfSRob Herring 233c15fddfSRob Herring The CoreSight Address Translation Unit (CATU) translates addresses between an 243c15fddfSRob Herring AXI master and system memory. The CATU is normally used along with the TMC to 253c15fddfSRob Herring implement scattering of virtual trace buffers in physical memory. The CATU 263c15fddfSRob Herring translates contiguous Virtual Addresses (VAs) from an AXI master into 273c15fddfSRob Herring non-contiguous Physical Addresses (PAs) that are intended for system memory. 283c15fddfSRob Herring 293c15fddfSRob Herring# Need a custom select here or 'arm,primecell' will match on lots of nodes 303c15fddfSRob Herringselect: 313c15fddfSRob Herring properties: 323c15fddfSRob Herring compatible: 333c15fddfSRob Herring contains: 343c15fddfSRob Herring const: arm,coresight-catu 353c15fddfSRob Herring required: 363c15fddfSRob Herring - compatible 373c15fddfSRob Herring 383c15fddfSRob HerringallOf: 393c15fddfSRob Herring - $ref: /schemas/arm/primecell.yaml# 403c15fddfSRob Herring 413c15fddfSRob Herringproperties: 423c15fddfSRob Herring compatible: 433c15fddfSRob Herring items: 443c15fddfSRob Herring - const: arm,coresight-catu 453c15fddfSRob Herring - const: arm,primecell 463c15fddfSRob Herring 473c15fddfSRob Herring reg: 483c15fddfSRob Herring maxItems: 1 493c15fddfSRob Herring 503c15fddfSRob Herring clocks: 513c15fddfSRob Herring minItems: 1 523c15fddfSRob Herring maxItems: 2 533c15fddfSRob Herring 543c15fddfSRob Herring clock-names: 553c15fddfSRob Herring minItems: 1 563c15fddfSRob Herring items: 573c15fddfSRob Herring - const: apb_pclk 583c15fddfSRob Herring - const: atclk 593c15fddfSRob Herring 603c15fddfSRob Herring interrupts: 613c15fddfSRob Herring maxItems: 1 623c15fddfSRob Herring description: Address translation error interrupt 633c15fddfSRob Herring 64*8559e62cSRob Herring power-domains: 65*8559e62cSRob Herring maxItems: 1 66*8559e62cSRob Herring 673c15fddfSRob Herring in-ports: 683c15fddfSRob Herring $ref: /schemas/graph.yaml#/properties/ports 693c15fddfSRob Herring additionalProperties: false 703c15fddfSRob Herring 713c15fddfSRob Herring properties: 723c15fddfSRob Herring port: 733c15fddfSRob Herring description: AXI Slave connected to another Coresight component 743c15fddfSRob Herring $ref: /schemas/graph.yaml#/properties/port 753c15fddfSRob Herring 763c15fddfSRob Herringrequired: 773c15fddfSRob Herring - compatible 783c15fddfSRob Herring - reg 793c15fddfSRob Herring - clocks 803c15fddfSRob Herring - clock-names 813c15fddfSRob Herring - in-ports 823c15fddfSRob Herring 833c15fddfSRob HerringunevaluatedProperties: false 843c15fddfSRob Herring 853c15fddfSRob Herringexamples: 863c15fddfSRob Herring - | 873c15fddfSRob Herring #include <dt-bindings/interrupt-controller/arm-gic.h> 883c15fddfSRob Herring catu@207e0000 { 893c15fddfSRob Herring compatible = "arm,coresight-catu", "arm,primecell"; 903c15fddfSRob Herring reg = <0x207e0000 0x1000>; 913c15fddfSRob Herring 923c15fddfSRob Herring clocks = <&oscclk6a>; 933c15fddfSRob Herring clock-names = "apb_pclk"; 943c15fddfSRob Herring 953c15fddfSRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 963c15fddfSRob Herring in-ports { 973c15fddfSRob Herring port { 983c15fddfSRob Herring catu_in_port: endpoint { 993c15fddfSRob Herring remote-endpoint = <&etr_out_port>; 1003c15fddfSRob Herring }; 1013c15fddfSRob Herring }; 1023c15fddfSRob Herring }; 1033c15fddfSRob Herring }; 1043c15fddfSRob Herring... 105