1*e97c6182SEugen Hristev# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*e97c6182SEugen Hristev%YAML 1.2 3*e97c6182SEugen Hristev--- 4*e97c6182SEugen Hristev$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml# 5*e97c6182SEugen Hristev$schema: http://devicetree.org/meta-schemas/core.yaml# 6*e97c6182SEugen Hristev 7*e97c6182SEugen Hristevtitle: MediaTek AUDSYS controller 8*e97c6182SEugen Hristev 9*e97c6182SEugen Hristevmaintainers: 10*e97c6182SEugen Hristev - Eugen Hristev <eugen.hristev@collabora.com> 11*e97c6182SEugen Hristev 12*e97c6182SEugen Hristevdescription: 13*e97c6182SEugen Hristev The MediaTek AUDSYS controller provides various clocks to the system. 14*e97c6182SEugen Hristev 15*e97c6182SEugen Hristevproperties: 16*e97c6182SEugen Hristev compatible: 17*e97c6182SEugen Hristev oneOf: 18*e97c6182SEugen Hristev - items: 19*e97c6182SEugen Hristev - enum: 20*e97c6182SEugen Hristev - mediatek,mt2701-audsys 21*e97c6182SEugen Hristev - mediatek,mt6765-audsys 22*e97c6182SEugen Hristev - mediatek,mt6779-audsys 23*e97c6182SEugen Hristev - mediatek,mt7622-audsys 24*e97c6182SEugen Hristev - mediatek,mt8167-audsys 25*e97c6182SEugen Hristev - mediatek,mt8173-audsys 26*e97c6182SEugen Hristev - mediatek,mt8183-audsys 27*e97c6182SEugen Hristev - mediatek,mt8186-audsys 28*e97c6182SEugen Hristev - mediatek,mt8192-audsys 29*e97c6182SEugen Hristev - mediatek,mt8516-audsys 30*e97c6182SEugen Hristev - const: syscon 31*e97c6182SEugen Hristev - items: 32*e97c6182SEugen Hristev # Special case for mt7623 for backward compatibility 33*e97c6182SEugen Hristev - const: mediatek,mt7623-audsys 34*e97c6182SEugen Hristev - const: mediatek,mt2701-audsys 35*e97c6182SEugen Hristev - const: syscon 36*e97c6182SEugen Hristev 37*e97c6182SEugen Hristev reg: 38*e97c6182SEugen Hristev maxItems: 1 39*e97c6182SEugen Hristev 40*e97c6182SEugen Hristev '#clock-cells': 41*e97c6182SEugen Hristev const: 1 42*e97c6182SEugen Hristev 43*e97c6182SEugen Hristev audio-controller: 44*e97c6182SEugen Hristev $ref: /schemas/sound/mediatek,mt2701-audio.yaml# 45*e97c6182SEugen Hristev type: object 46*e97c6182SEugen Hristev 47*e97c6182SEugen Hristevrequired: 48*e97c6182SEugen Hristev - compatible 49*e97c6182SEugen Hristev - '#clock-cells' 50*e97c6182SEugen Hristev 51*e97c6182SEugen HristevadditionalProperties: false 52*e97c6182SEugen Hristev 53*e97c6182SEugen Hristevexamples: 54*e97c6182SEugen Hristev - | 55*e97c6182SEugen Hristev #include <dt-bindings/interrupt-controller/arm-gic.h> 56*e97c6182SEugen Hristev #include <dt-bindings/interrupt-controller/irq.h> 57*e97c6182SEugen Hristev #include <dt-bindings/power/mt2701-power.h> 58*e97c6182SEugen Hristev #include <dt-bindings/clock/mt2701-clk.h> 59*e97c6182SEugen Hristev soc { 60*e97c6182SEugen Hristev #address-cells = <2>; 61*e97c6182SEugen Hristev #size-cells = <2>; 62*e97c6182SEugen Hristev audsys: clock-controller@11220000 { 63*e97c6182SEugen Hristev compatible = "mediatek,mt7622-audsys", "syscon"; 64*e97c6182SEugen Hristev reg = <0 0x11220000 0 0x2000>; 65*e97c6182SEugen Hristev #clock-cells = <1>; 66*e97c6182SEugen Hristev 67*e97c6182SEugen Hristev afe: audio-controller { 68*e97c6182SEugen Hristev compatible = "mediatek,mt2701-audio"; 69*e97c6182SEugen Hristev interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 70*e97c6182SEugen Hristev <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 71*e97c6182SEugen Hristev interrupt-names = "afe", "asys"; 72*e97c6182SEugen Hristev power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 73*e97c6182SEugen Hristev 74*e97c6182SEugen Hristev clocks = <&infracfg CLK_INFRA_AUDIO>, 75*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_MUX1_SEL>, 76*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_MUX2_SEL>, 77*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_48K_TIMING>, 78*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_44K_TIMING>, 79*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, 80*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, 81*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, 82*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, 83*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, 84*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, 85*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, 86*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, 87*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_I2S1_MCLK>, 88*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_I2S2_MCLK>, 89*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_I2S3_MCLK>, 90*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_I2S4_MCLK>, 91*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SO1>, 92*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SO2>, 93*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SO3>, 94*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SO4>, 95*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SIN1>, 96*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SIN2>, 97*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SIN3>, 98*e97c6182SEugen Hristev <&audsys CLK_AUD_I2SIN4>, 99*e97c6182SEugen Hristev <&audsys CLK_AUD_ASRCO1>, 100*e97c6182SEugen Hristev <&audsys CLK_AUD_ASRCO2>, 101*e97c6182SEugen Hristev <&audsys CLK_AUD_ASRCO3>, 102*e97c6182SEugen Hristev <&audsys CLK_AUD_ASRCO4>, 103*e97c6182SEugen Hristev <&audsys CLK_AUD_AFE>, 104*e97c6182SEugen Hristev <&audsys CLK_AUD_AFE_CONN>, 105*e97c6182SEugen Hristev <&audsys CLK_AUD_A1SYS>, 106*e97c6182SEugen Hristev <&audsys CLK_AUD_A2SYS>, 107*e97c6182SEugen Hristev <&audsys CLK_AUD_AFE_MRGIF>; 108*e97c6182SEugen Hristev 109*e97c6182SEugen Hristev clock-names = "infra_sys_audio_clk", 110*e97c6182SEugen Hristev "top_audio_mux1_sel", 111*e97c6182SEugen Hristev "top_audio_mux2_sel", 112*e97c6182SEugen Hristev "top_audio_a1sys_hp", 113*e97c6182SEugen Hristev "top_audio_a2sys_hp", 114*e97c6182SEugen Hristev "i2s0_src_sel", 115*e97c6182SEugen Hristev "i2s1_src_sel", 116*e97c6182SEugen Hristev "i2s2_src_sel", 117*e97c6182SEugen Hristev "i2s3_src_sel", 118*e97c6182SEugen Hristev "i2s0_src_div", 119*e97c6182SEugen Hristev "i2s1_src_div", 120*e97c6182SEugen Hristev "i2s2_src_div", 121*e97c6182SEugen Hristev "i2s3_src_div", 122*e97c6182SEugen Hristev "i2s0_mclk_en", 123*e97c6182SEugen Hristev "i2s1_mclk_en", 124*e97c6182SEugen Hristev "i2s2_mclk_en", 125*e97c6182SEugen Hristev "i2s3_mclk_en", 126*e97c6182SEugen Hristev "i2so0_hop_ck", 127*e97c6182SEugen Hristev "i2so1_hop_ck", 128*e97c6182SEugen Hristev "i2so2_hop_ck", 129*e97c6182SEugen Hristev "i2so3_hop_ck", 130*e97c6182SEugen Hristev "i2si0_hop_ck", 131*e97c6182SEugen Hristev "i2si1_hop_ck", 132*e97c6182SEugen Hristev "i2si2_hop_ck", 133*e97c6182SEugen Hristev "i2si3_hop_ck", 134*e97c6182SEugen Hristev "asrc0_out_ck", 135*e97c6182SEugen Hristev "asrc1_out_ck", 136*e97c6182SEugen Hristev "asrc2_out_ck", 137*e97c6182SEugen Hristev "asrc3_out_ck", 138*e97c6182SEugen Hristev "audio_afe_pd", 139*e97c6182SEugen Hristev "audio_afe_conn_pd", 140*e97c6182SEugen Hristev "audio_a1sys_pd", 141*e97c6182SEugen Hristev "audio_a2sys_pd", 142*e97c6182SEugen Hristev "audio_mrgif_pd"; 143*e97c6182SEugen Hristev 144*e97c6182SEugen Hristev assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, 145*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_MUX2_SEL>, 146*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_MUX1_DIV>, 147*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD_MUX2_DIV>; 148*e97c6182SEugen Hristev assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, 149*e97c6182SEugen Hristev <&topckgen CLK_TOP_AUD2PLL_90M>; 150*e97c6182SEugen Hristev assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; 151*e97c6182SEugen Hristev }; 152*e97c6182SEugen Hristev }; 153*e97c6182SEugen Hristev }; 154