1*eb522df4Sweiyi.lu@mediatek.comMediatek jpgdecsys controller 2*eb522df4Sweiyi.lu@mediatek.com============================ 3*eb522df4Sweiyi.lu@mediatek.com 4*eb522df4Sweiyi.lu@mediatek.comThe Mediatek jpgdecsys controller provides various clocks to the system. 5*eb522df4Sweiyi.lu@mediatek.com 6*eb522df4Sweiyi.lu@mediatek.comRequired Properties: 7*eb522df4Sweiyi.lu@mediatek.com 8*eb522df4Sweiyi.lu@mediatek.com- compatible: Should be: 9*eb522df4Sweiyi.lu@mediatek.com - "mediatek,mt2712-jpgdecsys", "syscon" 10*eb522df4Sweiyi.lu@mediatek.com- #clock-cells: Must be 1 11*eb522df4Sweiyi.lu@mediatek.com 12*eb522df4Sweiyi.lu@mediatek.comThe jpgdecsys controller uses the common clk binding from 13*eb522df4Sweiyi.lu@mediatek.comDocumentation/devicetree/bindings/clock/clock-bindings.txt 14*eb522df4Sweiyi.lu@mediatek.comThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 15*eb522df4Sweiyi.lu@mediatek.com 16*eb522df4Sweiyi.lu@mediatek.comExample: 17*eb522df4Sweiyi.lu@mediatek.com 18*eb522df4Sweiyi.lu@mediatek.comjpgdecsys: syscon@19000000 { 19*eb522df4Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 20*eb522df4Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 21*eb522df4Sweiyi.lu@mediatek.com #clock-cells = <1>; 22*eb522df4Sweiyi.lu@mediatek.com}; 23