1eb522df4Sweiyi.lu@mediatek.comMediatek mfgcfg controller 2eb522df4Sweiyi.lu@mediatek.com============================ 3eb522df4Sweiyi.lu@mediatek.com 4eb522df4Sweiyi.lu@mediatek.comThe Mediatek mfgcfg controller provides various clocks to the system. 5eb522df4Sweiyi.lu@mediatek.com 6eb522df4Sweiyi.lu@mediatek.comRequired Properties: 7eb522df4Sweiyi.lu@mediatek.com 8eb522df4Sweiyi.lu@mediatek.com- compatible: Should be one of: 9eb522df4Sweiyi.lu@mediatek.com - "mediatek,mt2712-mfgcfg", "syscon" 10171f68a3Smtk01761 - "mediatek,mt6779-mfgcfg", "syscon" 11*8adea9b9SFabien Parent - "mediatek,mt8167-mfgcfg", "syscon" 122f41cd9bSWeiyi Lu - "mediatek,mt8183-mfgcfg", "syscon" 13eb522df4Sweiyi.lu@mediatek.com- #clock-cells: Must be 1 14eb522df4Sweiyi.lu@mediatek.com 15eb522df4Sweiyi.lu@mediatek.comThe mfgcfg controller uses the common clk binding from 16eb522df4Sweiyi.lu@mediatek.comDocumentation/devicetree/bindings/clock/clock-bindings.txt 17eb522df4Sweiyi.lu@mediatek.comThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 18eb522df4Sweiyi.lu@mediatek.com 19eb522df4Sweiyi.lu@mediatek.comExample: 20eb522df4Sweiyi.lu@mediatek.com 21eb522df4Sweiyi.lu@mediatek.commfgcfg: syscon@13000000 { 22eb522df4Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 23eb522df4Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 24eb522df4Sweiyi.lu@mediatek.com #clock-cells = <1>; 25eb522df4Sweiyi.lu@mediatek.com}; 26