156618489SJames LiaoMediatek vdecsys controller 256618489SJames Liao============================ 356618489SJames Liao 456618489SJames LiaoThe Mediatek vdecsys controller provides various clocks to the system. 556618489SJames Liao 656618489SJames LiaoRequired Properties: 756618489SJames Liao 86a588703SJames Liao- compatible: Should be one of: 96a588703SJames Liao - "mediatek,mt2701-vdecsys", "syscon" 10eb522df4Sweiyi.lu@mediatek.com - "mediatek,mt2712-vdecsys", "syscon" 11171f68a3Smtk01761 - "mediatek,mt6779-vdecsys", "syscon" 122b51f514SKevin-CW Chen - "mediatek,mt6797-vdecsys", "syscon" 13fd2a9f18SMatthias Brugger - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon" 14*8adea9b9SFabien Parent - "mediatek,mt8167-vdecsys", "syscon" 1556618489SJames Liao - "mediatek,mt8173-vdecsys", "syscon" 162f41cd9bSWeiyi Lu - "mediatek,mt8183-vdecsys", "syscon" 1756618489SJames Liao- #clock-cells: Must be 1 1856618489SJames Liao 1956618489SJames LiaoThe vdecsys controller uses the common clk binding from 2056618489SJames LiaoDocumentation/devicetree/bindings/clock/clock-bindings.txt 2156618489SJames LiaoThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 2256618489SJames Liao 2356618489SJames LiaoExample: 2456618489SJames Liao 2556618489SJames Liaovdecsys: clock-controller@16000000 { 2656618489SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 2756618489SJames Liao reg = <0 0x16000000 0 0x1000>; 2856618489SJames Liao #clock-cells = <1>; 2956618489SJames Liao}; 30