1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A10 Module 0 Clock Device Tree Bindings
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13deprecated: true
14
15select:
16  properties:
17    compatible:
18      contains:
19        enum:
20          - allwinner,sun4i-a10-mod0-clk
21          - allwinner,sun9i-a80-mod0-clk
22
23  # The PRCM on the A31 and A23 will have the reg property missing,
24  # since it's set at the upper level node, and will be validated by
25  # PRCM's schema. Make sure we only validate standalone nodes.
26  required:
27    - compatible
28    - reg
29
30properties:
31  "#clock-cells":
32    const: 0
33
34  compatible:
35    enum:
36      - allwinner,sun4i-a10-mod0-clk
37      - allwinner,sun9i-a80-mod0-clk
38
39  reg:
40    maxItems: 1
41
42  clocks:
43    # On the A80, the PRCM mod0 clocks have 2 parents.
44    minItems: 2
45    maxItems: 3
46    description: >
47      The parent order must match the hardware programming order.
48
49  clock-output-names:
50    maxItems: 1
51
52required:
53  - "#clock-cells"
54  - compatible
55  - reg
56  - clocks
57  - clock-output-names
58
59additionalProperties: false
60
61examples:
62  - |
63    clk@1c20080 {
64        #clock-cells = <0>;
65        compatible = "allwinner,sun4i-a10-mod0-clk";
66        reg = <0x01c20080 0x4>;
67        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
68        clock-output-names = "nand";
69    };
70
71  - |
72    clk@8001454 {
73        #clock-cells = <0>;
74        compatible = "allwinner,sun4i-a10-mod0-clk";
75        reg = <0x08001454 0x4>;
76        clocks = <&osc32k>, <&osc24M>;
77        clock-output-names = "r_ir";
78    };
79
80...
81