1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
8
9maintainers:
10  - Melody Olvera <quic_molvera@quicinc.com>
11
12description: |
13  Qualcomm global clock control module which supports the clocks, resets and
14  power domains on QDU1000 and QRU1000
15
16  See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
17
18properties:
19  compatible:
20    const: qcom,qdu1000-gcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Sleep clock source
26      - description: PCIE 0 Pipe clock source
27      - description: PCIE 0 Phy Auxiliary clock source
28      - description: USB3 Phy wrapper pipe clock source
29
30required:
31  - compatible
32  - clocks
33
34allOf:
35  - $ref: qcom,gcc.yaml#
36
37unevaluatedProperties: false
38
39examples:
40  - |
41    #include <dt-bindings/clock/qcom,rpmh.h>
42    clock-controller@100000 {
43      compatible = "qcom,qdu1000-gcc";
44      reg = <0x00100000 0x001f4200>;
45      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
46               <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>,
47               <&usb3_phy_wrapper_pipe_clk>;
48      #clock-cells = <1>;
49      #reset-cells = <1>;
50      #power-domain-cells = <1>;
51    };
52