1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12description: |
13  The 5P35023 is a VersaClock programmable clock generator and
14  is designed for low-power, consumer, and high-performance PCI
15  express applications. The 5P35023 device is a three PLL
16  architecture design, and each PLL is individually programmable
17  and allowing for up to 6 unique frequency outputs.
18
19  An internal OTP memory allows the user to store the configuration
20  in the device. After power up, the user can change the device register
21  settings through the I2C interface when I2C mode is selected.
22
23  The driver can read a full register map from the DT, and will use that
24  register map to initialize the attached part (via I2C) when the system
25  boots. Any configuration not supported by the common clock framework
26  must be done via the full register map, including optimized settings.
27
28  Link to datasheet:
29  https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
30
31properties:
32  compatible:
33    enum:
34      - renesas,5p35023
35
36  reg:
37    maxItems: 1
38
39  '#clock-cells':
40    const: 1
41
42  clocks:
43    maxItems: 1
44
45  renesas,settings:
46    description: Optional, complete register map of the device.
47      Optimized settings for the device must be provided in full
48      and are written during initialization.
49    $ref: /schemas/types.yaml#/definitions/uint8-array
50    maxItems: 37
51
52required:
53  - compatible
54  - reg
55  - '#clock-cells'
56  - clocks
57
58additionalProperties: false
59
60examples:
61  - |
62    i2c {
63        #address-cells = <1>;
64        #size-cells = <0>;
65
66        versa3: clock-generator@68 {
67            compatible = "renesas,5p35023";
68            reg = <0x68>;
69            #clock-cells = <1>;
70
71            clocks = <&x1_x2>;
72
73            renesas,settings = [
74                80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
75                00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
76                80 b0 45 c4 95
77            ];
78
79            assigned-clocks = <&versa3 0>, <&versa3 1>,
80                              <&versa3 2>, <&versa3 3>,
81                              <&versa3 4>, <&versa3 5>;
82            assigned-clock-rates = <12288000>, <25000000>,
83                                   <12000000>, <11289600>,
84                                   <11289600>, <24000000>;
85        };
86    };
87