1Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator. 2 3Reference 4[1] Si5341 Data Sheet 5 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf 6[2] Si5341 Reference Manual 7 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf 8 9The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output 10clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which 11in turn can be directed to any of the 10 (or 4) outputs through a divider. 12The internal structure of the clock generators can be found in [2]. 13 14The driver can be used in "as is" mode, reading the current settings from the 15chip at boot, in case you have a (pre-)programmed device. If the PLL is not 16configured when the driver probes, it assumes the driver must fully initialize 17it. 18 19The device type, speed grade and revision are determined runtime by probing. 20 21The driver currently only supports XTAL input mode, and does not support any 22fancy input configurations. They can still be programmed into the chip and 23the driver will leave them "as is". 24 25==I2C device node== 26 27Required properties: 28- compatible: shall be one of the following: 29 "silabs,si5340" - Si5340 A/B/C/D 30 "silabs,si5341" - Si5341 A/B/C/D 31- reg: i2c device address, usually 0x74 32- #clock-cells: from common clock binding; shall be set to 2. 33 The first value is "0" for outputs, "1" for synthesizers. 34 The second value is the output or synthesizer index. 35- clocks: from common clock binding; list of parent clock handles, 36 corresponding to inputs. Use a fixed clock for the "xtal" input. 37 At least one must be present. 38- clock-names: One of: "xtal", "in0", "in1", "in2" 39- vdd-supply: Regulator node for VDD 40 41Optional properties: 42- vdda-supply: Regulator node for VDDA 43- vdds-supply: Regulator node for VDDS 44- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL 45 feedback divider. Must be such that the PLL output is in the valid range. For 46 example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only 47 the fraction matters, using 3500 and 12 will deliver the exact same result. 48 If these are not specified, and the PLL is not yet programmed when the driver 49 probes, the PLL will be set to 14GHz. 50- silabs,reprogram: When present, the driver will always assume the device must 51 be initialized, and always performs the soft-reset routine. Since this will 52 temporarily stop all output clocks, don't do this if the chip is generating 53 the CPU clock for example. 54- interrupts: Interrupt for INTRb pin. 55- #address-cells: shall be set to 1. 56- #size-cells: shall be set to 0. 57 58 59== Child nodes: Outputs == 60 61The child nodes list the output clocks. 62 63Each of the clock outputs can be overwritten individually by using a child node. 64If a child node for a clock output is not set, the configuration remains 65unchanged. 66 67Required child node properties: 68- reg: number of clock output. 69 70Optional child node properties: 71- vdd-supply: Regulator node for VDD for this output. The driver selects default 72 values for common-mode and amplitude based on the voltage. 73- silabs,format: Output format, one of: 74 1 = differential (defaults to LVDS levels) 75 2 = low-power (defaults to HCSL levels) 76 4 = LVCMOS 77- silabs,common-mode: Manually override output common mode, see [2] for values 78- silabs,amplitude: Manually override output amplitude, see [2] for values 79- silabs,synth-master: boolean. If present, this output is allowed to change the 80 multisynth frequency dynamically. 81- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH 82 when disabled, otherwise it's driven LOW. 83 84==Example== 85 86/* 48MHz reference crystal */ 87ref48: ref48M { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <48000000>; 91}; 92 93i2c-master-node { 94 /* Programmable clock (for logic) */ 95 si5341: clock-generator@74 { 96 reg = <0x74>; 97 compatible = "silabs,si5341"; 98 #clock-cells = <2>; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 clocks = <&ref48>; 102 clock-names = "xtal"; 103 104 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */ 105 silabs,pll-m-den = <48>; 106 silabs,reprogram; /* Chips are not programmed, always reset */ 107 108 out@0 { 109 reg = <0>; 110 silabs,format = <1>; /* LVDS 3v3 */ 111 silabs,common-mode = <3>; 112 silabs,amplitude = <3>; 113 silabs,synth-master; 114 }; 115 116 /* 117 * Output 6 configuration: 118 * LVDS 1v8 119 */ 120 out@6 { 121 reg = <6>; 122 silabs,format = <1>; /* LVDS 1v8 */ 123 silabs,common-mode = <13>; 124 silabs,amplitude = <3>; 125 }; 126 127 /* 128 * Output 8 configuration: 129 * HCSL 3v3 130 */ 131 out@8 { 132 reg = <8>; 133 silabs,format = <2>; 134 silabs,common-mode = <11>; 135 silabs,amplitude = <3>; 136 }; 137 }; 138}; 139 140some-video-node { 141 /* Standard clock bindings */ 142 clock-names = "pixel"; 143 clocks = <&si5341 0 7>; /* Output 7 */ 144 145 /* Set output 7 to use syntesizer 3 as its parent */ 146 assigned-clocks = <&si5341 0 7>, <&si5341 1 3>; 147 assigned-clock-parents = <&si5341 1 3>; 148 /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */ 149 assigned-clock-rates = <148500000>, <594000000>; 150}; 151 152some-audio-node { 153 clock-names = "i2s-clk"; 154 clocks = <&si5341 0 0>; 155 /* 156 * since output 0 is a synth-master, the synth will be automatically set 157 * to an appropriate frequency when the audio driver requests another 158 * frequency. We give control over synth 2 to this output here. 159 */ 160 assigned-clocks = <&si5341 0 0>; 161 assigned-clock-parents = <&si5341 1 2>; 162}; 163