1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Unleashed Rev C000 Platform DMA
8
9maintainers:
10  - Green Wan <green.wan@sifive.com>
11  - Palmer Debbelt <palmer@sifive.com>
12  - Paul Walmsley <paul.walmsley@sifive.com>
13
14description: |
15  Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
16  channels. Each channel has 2 interrupts. One is for DMA done and
17  the other is for DME error.
18
19  In different SoC, DMA could be attached to different IRQ line.
20  DT file need to be changed to meet the difference. For technical
21  doc,
22
23  https://static.dev.sifive.com/FU540-C000-v1.0.pdf
24
25allOf:
26  - $ref: dma-controller.yaml#
27
28properties:
29  compatible:
30    items:
31      - enum:
32          - microchip,mpfs-pdma
33          - sifive,fu540-c000-pdma
34      - const: sifive,pdma0
35    description:
36      Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
37      Supported compatible strings are -
38      "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
39      SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
40      with no chip integration tweaks.
41
42  reg:
43    maxItems: 1
44
45  interrupts:
46    minItems: 1
47    maxItems: 8
48
49  dma-channels:
50    description: For backwards-compatibility, the default value is 4
51    minimum: 1
52    maximum: 4
53    default: 4
54
55  '#dma-cells':
56    const: 1
57
58required:
59  - compatible
60  - reg
61  - interrupts
62
63unevaluatedProperties: false
64
65examples:
66  - |
67    dma-controller@3000000 {
68      compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
69      reg = <0x3000000 0x8000>;
70      dma-channels = <4>;
71      interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
72      #dma-cells = <1>;
73    };
74
75...
76