1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 DMA Controller bindings
8
9description: |
10  The STM32 DMA is a general-purpose direct memory access controller capable of
11  supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12  DMA clients connected to the STM32 DMA controller must use the format
13  described in the dma.txt file, using a four-cell specifier for each
14  channel: a phandle to the DMA controller plus the following four integer cells:
15    1. The channel id
16    2. The request line number
17    3. A 32bit mask specifying the DMA channel configuration which are device
18      dependent:
19        -bit 9: Peripheral Increment Address
20          0x0: no address increment between transfers
21          0x1: increment address between transfers
22        -bit 10: Memory Increment Address
23          0x0: no address increment between transfers
24          0x1: increment address between transfers
25        -bit 15: Peripheral Increment Offset Size
26          0x0: offset size is linked to the peripheral bus width
27          0x1: offset size is fixed to 4 (32-bit alignment)
28        -bit 16-17: Priority level
29          0x0: low
30          0x1: medium
31          0x2: high
32          0x3: very high
33    4. A 32bit bitfield value specifying DMA features which are device dependent:
34       -bit 0-1: DMA FIFO threshold selection
35         0x0: 1/4 full FIFO
36         0x1: 1/2 full FIFO
37         0x2: 3/4 full FIFO
38         0x3: full FIFO
39
40maintainers:
41  - Amelie Delaunay <amelie.delaunay@st.com>
42
43allOf:
44  - $ref: "dma-controller.yaml#"
45
46properties:
47  "#dma-cells":
48    const: 4
49
50  compatible:
51    const: st,stm32-dma
52
53  reg:
54    maxItems: 1
55
56  clocks:
57    maxItems: 1
58
59  interrupts:
60    maxItems: 8
61    description: Should contain all of the per-channel DMA
62      interrupts in ascending order with respect to the
63      DMA channel index.
64
65  resets:
66    maxItems: 1
67
68  st,mem2mem:
69    $ref: /schemas/types.yaml#/definitions/flag
70    description: if defined, it indicates that the controller
71      supports memory-to-memory transfer
72
73required:
74  - compatible
75  - reg
76  - clocks
77  - interrupts
78
79examples:
80  - |
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/clock/stm32mp1-clks.h>
83    #include <dt-bindings/reset/stm32mp1-resets.h>
84    dma-controller@40026400 {
85      compatible = "st,stm32-dma";
86      reg = <0x40026400 0x400>;
87      interrupts = <56>,
88                   <57>,
89                   <58>,
90                   <59>,
91                   <60>,
92                   <68>,
93                   <69>,
94                   <70>;
95      clocks = <&clk_hclk>;
96      #dma-cells = <4>;
97      st,mem2mem;
98      resets = <&rcc 150>;
99      dma-requests = <8>;
100    };
101
102...
103