1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated
3# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
4%YAML 1.2
5---
6$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: Texas Instruments K3 NAVSS Unified DMA
10
11maintainers:
12  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
13
14description: |
15  The UDMA-P is intended to perform similar (but significantly upgraded)
16  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
17  module supports the transmission and reception of various packet types.
18  The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
19  data structure compliant packets to/from smaller data blocks that are natively
20  compatible with the specific requirements of each connected peripheral.
21  Multiple Tx and Rx channels are provided within the DMA which allow multiple
22  segmentation or reassembly operations to be ongoing. The DMA controller
23  maintains state information for each of the channels which allows packet
24  segmentation and reassembly operations to be time division multiplexed between
25  channels in order to share the underlying DMA hardware. An external DMA
26  scheduler is used to control the ordering and rate at which this multiplexing
27  occurs for Transmit operations. The ordering and rate of Receive operations
28  is indirectly controlled by the order in which blocks are pushed into the DMA
29  on the Rx PSI-L interface.
30
31  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
32  channels. Channels in the UDMA-P can be configured to be either Packet-Based
33  or Third-Party channels on a channel by channel basis.
34
35  All transfers within NAVSS is done between PSI-L source and destination
36  threads.
37  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
38  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
39  is tasked to act as a bridge between the PSI-L fabric and the legacy
40  peripheral.
41
42  PDMAs can be configured via UDMAP peer registers to match with the
43  configuration of the legacy peripheral.
44
45allOf:
46  - $ref: "../dma-controller.yaml#"
47  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
48
49properties:
50  "#dma-cells":
51    minimum: 1
52    maximum: 2
53    description: |
54      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
55      Valid ranges for thread ID depends on the data movement direction:
56      for source thread IDs (rx): 0 - 0x7fff
57      for destination thread IDs (tx): 0x8000 - 0xffff
58
59      Please refer to the device documentation for the PSI-L thread map and also
60      the PSI-L peripheral chapter for the correct thread ID.
61
62      When #dma-cells is 2, the second parameter is the channel ATYPE.
63
64  compatible:
65    enum:
66      - ti,am654-navss-main-udmap
67      - ti,am654-navss-mcu-udmap
68      - ti,j721e-navss-main-udmap
69      - ti,j721e-navss-mcu-udmap
70
71  reg:
72    maxItems: 3
73
74  reg-names:
75    items:
76      - const: gcfg
77      - const: rchanrt
78      - const: tchanrt
79
80  msi-parent: true
81
82  ti,ringacc:
83    description: phandle to the ring accelerator node
84    $ref: /schemas/types.yaml#/definitions/phandle
85
86  ti,sci-rm-range-tchan:
87    description: |
88      Array of UDMA tchan resource subtypes for resource allocation for this
89      host
90    $ref: /schemas/types.yaml#/definitions/uint32-array
91    minItems: 1
92    # Should be enough
93    maxItems: 255
94
95  ti,sci-rm-range-rchan:
96    description: |
97      Array of UDMA rchan resource subtypes for resource allocation for this
98      host
99    $ref: /schemas/types.yaml#/definitions/uint32-array
100    minItems: 1
101    # Should be enough
102    maxItems: 255
103
104  ti,sci-rm-range-rflow:
105    description: |
106      Array of UDMA rflow resource subtypes for resource allocation for this
107      host
108    $ref: /schemas/types.yaml#/definitions/uint32-array
109    minItems: 1
110    # Should be enough
111    maxItems: 255
112
113required:
114  - compatible
115  - "#dma-cells"
116  - reg
117  - reg-names
118  - msi-parent
119  - ti,sci
120  - ti,sci-dev-id
121  - ti,ringacc
122  - ti,sci-rm-range-tchan
123  - ti,sci-rm-range-rchan
124  - ti,sci-rm-range-rflow
125
126if:
127  properties:
128    "#dma-cells":
129      const: 2
130then:
131  properties:
132    ti,udma-atype:
133      description: ATYPE value which should be used by non slave channels
134      $ref: /schemas/types.yaml#/definitions/uint32
135
136  required:
137    - ti,udma-atype
138
139unevaluatedProperties: false
140
141examples:
142  - |+
143    cbass_main {
144        #address-cells = <2>;
145        #size-cells = <2>;
146
147        cbass_main_navss: navss@30800000 {
148            compatible = "simple-mfd";
149            #address-cells = <2>;
150            #size-cells = <2>;
151            dma-coherent;
152            dma-ranges;
153            ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
154
155            ti,sci-dev-id = <118>;
156
157            main_udmap: dma-controller@31150000 {
158                compatible = "ti,am654-navss-main-udmap";
159                reg = <0x0 0x31150000 0x0 0x100>,
160                      <0x0 0x34000000 0x0 0x100000>,
161                      <0x0 0x35000000 0x0 0x100000>;
162                reg-names = "gcfg", "rchanrt", "tchanrt";
163                #dma-cells = <1>;
164
165                ti,ringacc = <&ringacc>;
166
167                msi-parent = <&inta_main_udmass>;
168
169                ti,sci = <&dmsc>;
170                ti,sci-dev-id = <188>;
171
172                ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
173                                        <0x2>; /* TX_CHAN */
174                ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
175                                        <0x5>; /* RX_CHAN */
176                ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
177            };
178        };
179    };
180