1*9a0d4404SChristian Lamparter* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs 2*9a0d4404SChristian Lamparter 3*9a0d4404SChristian LamparterAll GPIOs are pin-shared with other functions. DCRs control whether a 4*9a0d4404SChristian Lamparterparticular pin that has GPIO capabilities acts as a GPIO or is used for 5*9a0d4404SChristian Lamparteranother purpose. GPIO outputs are separately programmable to emulate 6*9a0d4404SChristian Lamparteran open-drain driver. 7*9a0d4404SChristian Lamparter 8*9a0d4404SChristian LamparterRequired properties: 9*9a0d4404SChristian Lamparter - compatible: must be "ibm,ppc4xx-gpio" 10*9a0d4404SChristian Lamparter - reg: address and length of the register set for the device 11*9a0d4404SChristian Lamparter - #gpio-cells: must be set to 2. The first cell is the pin number 12*9a0d4404SChristian Lamparter and the second cell is used to specify the gpio polarity: 13*9a0d4404SChristian Lamparter 0 = active high 14*9a0d4404SChristian Lamparter 1 = active low 15*9a0d4404SChristian Lamparter - gpio-controller: marks the device node as a gpio controller. 16*9a0d4404SChristian Lamparter 17*9a0d4404SChristian LamparterExample: 18*9a0d4404SChristian Lamparter 19*9a0d4404SChristian LamparterGPIO0: gpio@ef600b00 { 20*9a0d4404SChristian Lamparter compatible = "ibm,ppc4xx-gpio"; 21*9a0d4404SChristian Lamparter reg = <0xef600b00 0x00000048>; 22*9a0d4404SChristian Lamparter #gpio-cells = <2>; 23*9a0d4404SChristian Lamparter gpio-controller; 24*9a0d4404SChristian Lamparter}; 25