1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SMI (Smart Multimedia Interface) Common
9
10maintainers:
11  - Yong Wu <yong.wu@mediatek.com>
12
13description: |
14  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15
16  MediaTek SMI have two generations of HW architecture, here is the list
17  which generation the SoCs use:
18  generation 1: mt2701 and mt7623.
19  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
20
21  There's slight differences between the two SMI, for generation 2, the
22  register which control the iommu port is at each larb's register base. But
23  for generation 1, the register is at smi ao base(smi always on register
24  base). Besides that, the smi async clock should be prepared and enabled for
25  SMI generation 1 to transform the smi clock into emi clock domain, but that is
26  not needed for SMI generation 2.
27
28properties:
29  compatible:
30    oneOf:
31      - enum:
32          - mediatek,mt2701-smi-common
33          - mediatek,mt2712-smi-common
34          - mediatek,mt6779-smi-common
35          - mediatek,mt6795-smi-common
36          - mediatek,mt8167-smi-common
37          - mediatek,mt8173-smi-common
38          - mediatek,mt8183-smi-common
39          - mediatek,mt8186-smi-common
40          - mediatek,mt8188-smi-common-vdo
41          - mediatek,mt8188-smi-common-vpp
42          - mediatek,mt8192-smi-common
43          - mediatek,mt8195-smi-common-vdo
44          - mediatek,mt8195-smi-common-vpp
45          - mediatek,mt8195-smi-sub-common
46
47      - description: for mt7623
48        items:
49          - const: mediatek,mt7623-smi-common
50          - const: mediatek,mt2701-smi-common
51
52  reg:
53    maxItems: 1
54
55  power-domains:
56    maxItems: 1
57
58  clocks:
59    description: |
60      apb and smi are mandatory. the async is only for generation 1 smi HW.
61      gals(global async local sync) also is optional, see below.
62    minItems: 2
63    items:
64      - description: apb is Advanced Peripheral Bus clock, It's the clock for
65          setting the register.
66      - description: smi is the clock for transfer data and command.
67      - description: Either asynchronous clock to help transform the smi clock
68          into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
69      - description: gals1 is the path1 clock of gals.
70
71  clock-names:
72    minItems: 2
73    maxItems: 4
74
75  mediatek,smi:
76    $ref: /schemas/types.yaml#/definitions/phandle
77    description: a phandle to the smi-common node above. Only for sub-common.
78
79required:
80  - compatible
81  - reg
82  - power-domains
83  - clocks
84  - clock-names
85
86allOf:
87  - if:  # only for gen1 HW
88      properties:
89        compatible:
90          contains:
91            enum:
92              - mediatek,mt2701-smi-common
93    then:
94      properties:
95        clocks:
96          minItems: 3
97          maxItems: 3
98        clock-names:
99          items:
100            - const: apb
101            - const: smi
102            - const: async
103
104  - if:  # only for sub common
105      properties:
106        compatible:
107          contains:
108            enum:
109              - mediatek,mt8195-smi-sub-common
110    then:
111      required:
112        - mediatek,smi
113      properties:
114        clocks:
115          minItems: 3
116          maxItems: 3
117        clock-names:
118          items:
119            - const: apb
120            - const: smi
121            - const: gals0
122    else:
123      properties:
124        mediatek,smi: false
125
126  - if:  # for gen2 HW that have gals
127      properties:
128        compatible:
129          enum:
130            - mediatek,mt6779-smi-common
131            - mediatek,mt8183-smi-common
132            - mediatek,mt8186-smi-common
133            - mediatek,mt8192-smi-common
134            - mediatek,mt8195-smi-common-vdo
135            - mediatek,mt8195-smi-common-vpp
136
137    then:
138      properties:
139        clocks:
140          minItems: 4
141          maxItems: 4
142        clock-names:
143          items:
144            - const: apb
145            - const: smi
146            - const: gals0
147            - const: gals1
148
149  - if:  # for gen2 HW that don't have gals
150      properties:
151        compatible:
152          enum:
153            - mediatek,mt2712-smi-common
154            - mediatek,mt6795-smi-common
155            - mediatek,mt8167-smi-common
156            - mediatek,mt8173-smi-common
157
158    then:
159      properties:
160        clocks:
161          minItems: 2
162          maxItems: 2
163        clock-names:
164          items:
165            - const: apb
166            - const: smi
167
168additionalProperties: false
169
170examples:
171  - |+
172    #include <dt-bindings/clock/mt8173-clk.h>
173    #include <dt-bindings/power/mt8173-power.h>
174
175    smi_common: smi@14022000 {
176            compatible = "mediatek,mt8173-smi-common";
177            reg = <0x14022000 0x1000>;
178            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
179            clocks = <&mmsys CLK_MM_SMI_COMMON>,
180                     <&mmsys CLK_MM_SMI_COMMON>;
181            clock-names = "apb", "smi";
182    };
183