1# SPDX-License-Identifier: (GPL-2.0)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra30 SoC Memory Controller
8
9maintainers:
10  - Dmitry Osipenko <digetx@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Thierry Reding <thierry.reding@gmail.com>
13
14description: |
15  Tegra30 Memory Controller architecturally consists of the following parts:
16
17    Arbitration Domains, which can handle a single request or response per
18    clock from a group of clients. Typically, a system has a single Arbitration
19    Domain, but an implementation may divide the client space into multiple
20    Arbitration Domains to increase the effective system bandwidth.
21
22    Protocol Arbiter, which manage a related pool of memory devices. A system
23    may have a single Protocol Arbiter or multiple Protocol Arbiters.
24
25    Memory Crossbar, which routes request and responses between Arbitration
26    Domains and Protocol Arbiters. In the simplest version of the system, the
27    Memory Crossbar is just a pass through between a single Arbitration Domain
28    and a single Protocol Arbiter.
29
30    Global Resources, which include things like configuration registers which
31    are shared across the Memory Subsystem.
32
33  The Tegra30 Memory Controller handles memory requests from internal clients
34  and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
35  SDRAMs.
36
37properties:
38  compatible:
39    const: nvidia,tegra30-mc
40
41  reg:
42    maxItems: 1
43
44  clocks:
45    maxItems: 1
46
47  clock-names:
48    items:
49      - const: mc
50
51  interrupts:
52    maxItems: 1
53
54  "#reset-cells":
55    const: 1
56
57  "#iommu-cells":
58    const: 1
59
60patternProperties:
61  "^emc-timings-[0-9]+$":
62    type: object
63    properties:
64      nvidia,ram-code:
65        $ref: /schemas/types.yaml#/definitions/uint32
66        description:
67          Value of RAM_CODE this timing set is used for.
68
69    patternProperties:
70      "^timing-[0-9]+$":
71        type: object
72        properties:
73          clock-frequency:
74            description:
75              Memory clock rate in Hz.
76            minimum: 1000000
77            maximum: 900000000
78
79          nvidia,emem-configuration:
80            allOf:
81              - $ref: /schemas/types.yaml#/definitions/uint32-array
82            description: |
83              Values to be written to the EMEM register block. See section
84              "18.13.1 MC Registers" in the TRM.
85            items:
86              - description: MC_EMEM_ARB_CFG
87              - description: MC_EMEM_ARB_OUTSTANDING_REQ
88              - description: MC_EMEM_ARB_TIMING_RCD
89              - description: MC_EMEM_ARB_TIMING_RP
90              - description: MC_EMEM_ARB_TIMING_RC
91              - description: MC_EMEM_ARB_TIMING_RAS
92              - description: MC_EMEM_ARB_TIMING_FAW
93              - description: MC_EMEM_ARB_TIMING_RRD
94              - description: MC_EMEM_ARB_TIMING_RAP2PRE
95              - description: MC_EMEM_ARB_TIMING_WAP2PRE
96              - description: MC_EMEM_ARB_TIMING_R2R
97              - description: MC_EMEM_ARB_TIMING_W2W
98              - description: MC_EMEM_ARB_TIMING_R2W
99              - description: MC_EMEM_ARB_TIMING_W2R
100              - description: MC_EMEM_ARB_DA_TURNS
101              - description: MC_EMEM_ARB_DA_COVERS
102              - description: MC_EMEM_ARB_MISC0
103              - description: MC_EMEM_ARB_RING1_THROTTLE
104
105        required:
106          - clock-frequency
107          - nvidia,emem-configuration
108
109        additionalProperties: false
110
111    required:
112      - nvidia,ram-code
113
114    additionalProperties: false
115
116required:
117  - compatible
118  - reg
119  - interrupts
120  - clocks
121  - clock-names
122  - "#reset-cells"
123  - "#iommu-cells"
124
125additionalProperties: false
126
127examples:
128  - |
129    memory-controller@7000f000 {
130        compatible = "nvidia,tegra30-mc";
131        reg = <0x7000f000 0x400>;
132        clocks = <&tegra_car 32>;
133        clock-names = "mc";
134
135        interrupts = <0 77 4>;
136
137        #iommu-cells = <1>;
138        #reset-cells = <1>;
139
140        emc-timings-1 {
141            nvidia,ram-code = <1>;
142
143            timing-667000000 {
144                clock-frequency = <667000000>;
145
146                nvidia,emem-configuration = <
147                    0x0000000a /* MC_EMEM_ARB_CFG */
148                    0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
149                    0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
150                    0x00000004 /* MC_EMEM_ARB_TIMING_RP */
151                    0x00000010 /* MC_EMEM_ARB_TIMING_RC */
152                    0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
153                    0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
154                    0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
155                    0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
156                    0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
157                    0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
158                    0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
159                    0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
160                    0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
161                    0x08040202 /* MC_EMEM_ARB_DA_TURNS */
162                    0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
163                    0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
164                    0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
165                >;
166            };
167        };
168    };
169