1e5e3dea8SLaxman DewanganMAX77620 Power management IC from Maxim Semiconductor. 2e5e3dea8SLaxman Dewangan 3e5e3dea8SLaxman DewanganRequired properties: 4e5e3dea8SLaxman Dewangan------------------- 5e5e3dea8SLaxman Dewangan- compatible: Must be one of 6e5e3dea8SLaxman Dewangan "maxim,max77620" 756076a53SDmitry Osipenko "maxim,max20024" 856076a53SDmitry Osipenko "maxim,max77663" 9e5e3dea8SLaxman Dewangan- reg: I2C device address. 10e5e3dea8SLaxman Dewangan 11e5e3dea8SLaxman DewanganOptional properties: 12e5e3dea8SLaxman Dewangan------------------- 13e5e3dea8SLaxman Dewangan- interrupts: The interrupt on the parent the controller is 14e5e3dea8SLaxman Dewangan connected to. 15e5e3dea8SLaxman Dewangan- interrupt-controller: Marks the device node as an interrupt controller. 16e5e3dea8SLaxman Dewangan- #interrupt-cells: is <2> and their usage is compliant to the 2 cells 17e5e3dea8SLaxman Dewangan variant of <../interrupt-controller/interrupts.txt> 18e5e3dea8SLaxman Dewangan IRQ numbers for different interrupt source of MAX77620 19e5e3dea8SLaxman Dewangan are defined at dt-bindings/mfd/max77620.h. 20e5e3dea8SLaxman Dewangan 21*c63217a4SDmitry Osipenko- system-power-controller: Indicates that this PMIC is controlling the 22*c63217a4SDmitry Osipenko system power, see [1] for more details. 23*c63217a4SDmitry Osipenko 24*c63217a4SDmitry Osipenko[1] Documentation/devicetree/bindings/power/power-controller.txt 25*c63217a4SDmitry Osipenko 26e5e3dea8SLaxman DewanganOptional subnodes and their properties: 27e5e3dea8SLaxman Dewangan======================================= 28e5e3dea8SLaxman Dewangan 29e5e3dea8SLaxman DewanganFlexible power sequence configurations: 30e5e3dea8SLaxman Dewangan-------------------------------------- 31e5e3dea8SLaxman DewanganThe Flexible Power Sequencer (FPS) allows each regulator to power up under 32e5e3dea8SLaxman Dewanganhardware or software control. Additionally, each regulator can power on 33e5e3dea8SLaxman Dewanganindependently or among a group of other regulators with an adjustable power-up 34e5e3dea8SLaxman Dewanganand power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed 35e5e3dea8SLaxman Dewanganto be part of a sequence allowing external regulators to be sequenced along 36e5e3dea8SLaxman Dewanganwith internal regulators. 32KHz clock can be programmed to be part of a 37e5e3dea8SLaxman Dewangansequence. 38e5e3dea8SLaxman Dewangan 39e5e3dea8SLaxman DewanganThe flexible sequencing structure consists of two hardware enable inputs 40e5e3dea8SLaxman Dewangan(EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2. 41e5e3dea8SLaxman DewanganEach master sequencing timer is programmable through its configuration 42e5e3dea8SLaxman Dewanganregister to have a hardware enable source (EN1 or EN2) or a software enable 43e5e3dea8SLaxman Dewangansource (SW). When enabled/disabled, the master sequencing timer generates 44e5e3dea8SLaxman Dewanganeight sequencing events on different time periods called slots. The time 45e5e3dea8SLaxman Dewanganperiod between each event is programmable within the configuration register. 46e5e3dea8SLaxman DewanganEach regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power 47e5e3dea8SLaxman Dewangansequence slave register which allows its enable source to be specified as 48e5e3dea8SLaxman Dewangana flexible power sequencer timer or a software bit. When a FPS source of 49e5e3dea8SLaxman Dewanganregulators, GPIOs and clocks specifies the enable source to be a flexible 50e5e3dea8SLaxman Dewanganpower sequencer, the power up and power down delays can be specified in 51e5e3dea8SLaxman Dewanganthe regulators, GPIOs and clocks flexible power sequencer configuration 52e5e3dea8SLaxman Dewanganregisters. 53e5e3dea8SLaxman Dewangan 54e5e3dea8SLaxman DewanganWhen FPS event cleared (set to LOW), regulators, GPIOs and 32KHz 55e5e3dea8SLaxman Dewanganclock are set into following state at the sequencing event that 56e5e3dea8SLaxman Dewangancorresponds to its flexible sequencer configuration register. 57e5e3dea8SLaxman Dewangan Sleep state: In this state, regulators, GPIOs 58e5e3dea8SLaxman Dewangan and 32KHz clock get disabled at 59e5e3dea8SLaxman Dewangan the sequencing event. 60e5e3dea8SLaxman Dewangan Global Low Power Mode (GLPM): In this state, regulators are set in 61e5e3dea8SLaxman Dewangan low power mode at the sequencing event. 62e5e3dea8SLaxman Dewangan 63e5e3dea8SLaxman DewanganThe configuration parameters of FPS is provided through sub-node "fps" 64e5e3dea8SLaxman Dewanganand their child for FPS specific. The child node name for FPS are "fps0", 65e5e3dea8SLaxman Dewangan"fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively. 66e5e3dea8SLaxman Dewangan 67e5e3dea8SLaxman DewanganThe FPS configurations like FPS source, power up and power down slots for 68e5e3dea8SLaxman Dewanganregulators, GPIOs and 32kHz clocks are provided in their respective 69e5e3dea8SLaxman Dewanganconfiguration nodes which is explained in respective sub-system DT 70e5e3dea8SLaxman Dewanganbinding document. 71e5e3dea8SLaxman Dewangan 72e5e3dea8SLaxman DewanganThere is need for different FPS configuration parameters based on system 73e5e3dea8SLaxman Dewanganstate like when system state changed from active to suspend or active to 74e5e3dea8SLaxman Dewanganpower off (shutdown). 75e5e3dea8SLaxman Dewangan 76e5e3dea8SLaxman DewanganOptional properties: 77e5e3dea8SLaxman Dewangan------------------- 78e5e3dea8SLaxman Dewangan-maxim,fps-event-source: u32, FPS event source like external 79e5e3dea8SLaxman Dewangan hardware input to PMIC i.e. EN0, EN1 or 80e5e3dea8SLaxman Dewangan software (SW). 81e5e3dea8SLaxman Dewangan The macros are defined on 82e5e3dea8SLaxman Dewangan dt-bindings/mfd/max77620.h 83e5e3dea8SLaxman Dewangan for different control source. 84e5e3dea8SLaxman Dewangan - MAX77620_FPS_EVENT_SRC_EN0 85e5e3dea8SLaxman Dewangan for hardware input pin EN0. 86e5e3dea8SLaxman Dewangan - MAX77620_FPS_EVENT_SRC_EN1 87e5e3dea8SLaxman Dewangan for hardware input pin EN1. 88e5e3dea8SLaxman Dewangan - MAX77620_FPS_EVENT_SRC_SW 89e5e3dea8SLaxman Dewangan for software control. 90e5e3dea8SLaxman Dewangan 91e5e3dea8SLaxman Dewangan-maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds 92e5e3dea8SLaxman Dewangan when system enters in to shutdown 93e5e3dea8SLaxman Dewangan state. 94e5e3dea8SLaxman Dewangan 95e5e3dea8SLaxman Dewangan-maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds 96e5e3dea8SLaxman Dewangan when system enters in to suspend state. 97e5e3dea8SLaxman Dewangan 98e5e3dea8SLaxman Dewangan-maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS 99e5e3dea8SLaxman Dewangan event cleared (set to LOW) whether it 100e5e3dea8SLaxman Dewangan should go to sleep state or low-power 101e5e3dea8SLaxman Dewangan state. Following are valid values: 102e5e3dea8SLaxman Dewangan - MAX77620_FPS_INACTIVE_STATE_SLEEP 103e5e3dea8SLaxman Dewangan to set the PMIC state to sleep. 104e5e3dea8SLaxman Dewangan - MAX77620_FPS_INACTIVE_STATE_LOW_POWER 105e5e3dea8SLaxman Dewangan to set the PMIC state to low 106e5e3dea8SLaxman Dewangan power. 107e5e3dea8SLaxman Dewangan Absence of this property or other value 108e5e3dea8SLaxman Dewangan will not change device state when FPS 109e5e3dea8SLaxman Dewangan event get cleared. 110e5e3dea8SLaxman Dewangan 111e5e3dea8SLaxman DewanganHere supported time periods by device in microseconds are as follows: 112e5e3dea8SLaxman DewanganMAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds. 113e5e3dea8SLaxman DewanganMAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds. 11456076a53SDmitry OsipenkoMAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds. 115e5e3dea8SLaxman Dewangan 11698377923SVenkat Reddy Talla-maxim,power-ok-control: configure map power ok bit 11798377923SVenkat Reddy Talla 1: Enables POK(Power OK) to control nRST_IO and GPIO1 11898377923SVenkat Reddy Talla POK function. 11998377923SVenkat Reddy Talla 0: Disables POK control. 12098377923SVenkat Reddy Talla if property missing, do not configure MPOK bit. 12198377923SVenkat Reddy Talla If POK mapping is enabled for GPIO1/nRST_IO then, 12298377923SVenkat Reddy Talla GPIO1/nRST_IO pins are HIGH only if all rails 12398377923SVenkat Reddy Talla that have POK control enabled are HIGH. 12498377923SVenkat Reddy Talla If any of the rails goes down(which are enabled for POK 12598377923SVenkat Reddy Talla control) then, GPIO1/nRST_IO goes LOW. 12698377923SVenkat Reddy Talla this property is valid for max20024 only. 12798377923SVenkat Reddy Talla 128e5e3dea8SLaxman DewanganFor DT binding details of different sub modules like GPIO, pincontrol, 129e5e3dea8SLaxman Dewanganregulator, power, please refer respective device-tree binding document 130e5e3dea8SLaxman Dewanganunder their respective sub-system directories. 131e5e3dea8SLaxman Dewangan 132e5e3dea8SLaxman DewanganExample: 133e5e3dea8SLaxman Dewangan-------- 134e5e3dea8SLaxman Dewangan#include <dt-bindings/mfd/max77620.h> 135e5e3dea8SLaxman Dewangan 136e5e3dea8SLaxman Dewanganmax77620@3c { 137e5e3dea8SLaxman Dewangan compatible = "maxim,max77620"; 138e5e3dea8SLaxman Dewangan reg = <0x3c>; 139e5e3dea8SLaxman Dewangan 140e5e3dea8SLaxman Dewangan interrupt-parent = <&intc>; 141e5e3dea8SLaxman Dewangan interrupts = <0 86 IRQ_TYPE_NONE>; 142e5e3dea8SLaxman Dewangan 143e5e3dea8SLaxman Dewangan interrupt-controller; 144e5e3dea8SLaxman Dewangan #interrupt-cells = <2>; 145e5e3dea8SLaxman Dewangan 146e5e3dea8SLaxman Dewangan fps { 147e5e3dea8SLaxman Dewangan fps0 { 148e5e3dea8SLaxman Dewangan maxim,shutdown-fps-time-period-us = <1280>; 149e5e3dea8SLaxman Dewangan maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 150e5e3dea8SLaxman Dewangan }; 151e5e3dea8SLaxman Dewangan 152e5e3dea8SLaxman Dewangan fps1 { 153e5e3dea8SLaxman Dewangan maxim,shutdown-fps-time-period-us = <1280>; 154e5e3dea8SLaxman Dewangan maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 155e5e3dea8SLaxman Dewangan }; 156e5e3dea8SLaxman Dewangan 157e5e3dea8SLaxman Dewangan fps2 { 158e5e3dea8SLaxman Dewangan maxim,shutdown-fps-time-period-us = <1280>; 159e5e3dea8SLaxman Dewangan maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>; 160e5e3dea8SLaxman Dewangan }; 161e5e3dea8SLaxman Dewangan }; 162e5e3dea8SLaxman Dewangan}; 163