1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller Binding
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt2701-mmc
21          - mediatek,mt2712-mmc
22          - mediatek,mt6779-mmc
23          - mediatek,mt7620-mmc
24          - mediatek,mt7622-mmc
25          - mediatek,mt8135-mmc
26          - mediatek,mt8173-mmc
27          - mediatek,mt8183-mmc
28          - mediatek,mt8516-mmc
29      - items:
30          - const: mediatek,mt7623-mmc
31          - const: mediatek,mt2701-mmc
32      - items:
33          - const: mediatek,mt8186-mmc
34          - const: mediatek,mt8183-mmc
35      - items:
36          - const: mediatek,mt8192-mmc
37          - const: mediatek,mt8183-mmc
38      - items:
39          - const: mediatek,mt8195-mmc
40          - const: mediatek,mt8183-mmc
41
42  reg:
43    minItems: 1
44    items:
45      - description: base register (required).
46      - description: top base register (required for MT8183).
47
48  clocks:
49    description:
50      Should contain phandle for the clock feeding the MMC controller.
51    minItems: 2
52    items:
53      - description: source clock (required).
54      - description: HCLK which used for host (required).
55      - description: independent source clock gate (required for MT2712).
56      - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
57      - description: msdc subsys clock gate (required for MT8192).
58      - description: peripheral bus clock gate (required for MT8192).
59      - description: AXI bus clock gate (required for MT8192).
60      - description: AHB bus clock gate (required for MT8192).
61
62  clock-names:
63    minItems: 2
64    items:
65      - const: source
66      - const: hclk
67      - const: source_cg
68      - const: bus_clk
69      - const: sys_cg
70      - const: pclk_cg
71      - const: axi_cg
72      - const: ahb_cg
73
74  interrupts:
75    maxItems: 1
76
77  pinctrl-names:
78    items:
79      - const: default
80      - const: state_uhs
81
82  pinctrl-0:
83    description:
84      should contain default/high speed pin ctrl.
85    maxItems: 1
86
87  pinctrl-1:
88    description:
89      should contain uhs mode pin ctrl.
90    maxItems: 1
91
92  assigned-clocks:
93    description:
94      PLL of the source clock.
95    maxItems: 1
96
97  assigned-clock-parents:
98    description:
99      parent of source clock, used for HS400 mode to get 400Mhz source clock.
100    maxItems: 1
101
102  hs400-ds-delay:
103    $ref: /schemas/types.yaml#/definitions/uint32
104    description:
105      HS400 DS delay setting.
106    minimum: 0
107    maximum: 0xffffffff
108
109  mediatek,hs200-cmd-int-delay:
110    $ref: /schemas/types.yaml#/definitions/uint32
111    description:
112      HS200 command internal delay setting.
113      This field has total 32 stages.
114      The value is an integer from 0 to 31.
115    minimum: 0
116    maximum: 31
117
118  mediatek,hs400-cmd-int-delay:
119    $ref: /schemas/types.yaml#/definitions/uint32
120    description:
121      HS400 command internal delay setting.
122      This field has total 32 stages.
123      The value is an integer from 0 to 31.
124    minimum: 0
125    maximum: 31
126
127  mediatek,hs400-cmd-resp-sel-rising:
128    $ref: /schemas/types.yaml#/definitions/flag
129    description:
130      HS400 command response sample selection.
131      If present, HS400 command responses are sampled on rising edges.
132      If not present, HS400 command responses are sampled on falling edges.
133
134  mediatek,hs400-ds-dly3:
135    $ref: /schemas/types.yaml#/definitions/uint32
136    description:
137      Gear of the third delay line for DS for input data latch in data
138      pad macro, there are 32 stages from 0 to 31.
139      For different corner IC, the time is different about one step, it is
140      about 100ps.
141      The value is confirmed by doing scan and calibration to find a best
142      value with corner IC and it is valid only for HS400 mode.
143    minimum: 0
144    maximum: 31
145
146  mediatek,latch-ck:
147    $ref: /schemas/types.yaml#/definitions/uint32
148    description:
149      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
150      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
151      if not present, default value is 0.
152      applied to compatible "mediatek,mt2701-mmc".
153    minimum: 0
154    maximum: 7
155
156  resets:
157    maxItems: 1
158
159  reset-names:
160    const: hrst
161
162required:
163  - compatible
164  - reg
165  - interrupts
166  - clocks
167  - clock-names
168  - pinctrl-names
169  - pinctrl-0
170  - pinctrl-1
171  - vmmc-supply
172  - vqmmc-supply
173
174if:
175  properties:
176    compatible:
177      contains:
178        const: mediatek,mt8183-mmc
179then:
180  properties:
181    reg:
182      minItems: 2
183
184unevaluatedProperties: false
185
186examples:
187  - |
188    #include <dt-bindings/interrupt-controller/irq.h>
189    #include <dt-bindings/interrupt-controller/arm-gic.h>
190    #include <dt-bindings/clock/mt8173-clk.h>
191    mmc0: mmc@11230000 {
192        compatible = "mediatek,mt8173-mmc";
193        reg = <0x11230000 0x1000>;
194        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
195        vmmc-supply = <&mt6397_vemc_3v3_reg>;
196        vqmmc-supply = <&mt6397_vio18_reg>;
197        clocks = <&pericfg CLK_PERI_MSDC30_0>,
198                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
199        clock-names = "source", "hclk";
200        pinctrl-names = "default", "state_uhs";
201        pinctrl-0 = <&mmc0_pins_default>;
202        pinctrl-1 = <&mmc0_pins_uhs>;
203        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
204        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
205        hs400-ds-delay = <0x14015>;
206        mediatek,hs200-cmd-int-delay = <26>;
207        mediatek,hs400-cmd-int-delay = <14>;
208        mediatek,hs400-cmd-resp-sel-rising;
209    };
210
211...
212