1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller Binding
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - mediatek,mt2701-mmc
21          - mediatek,mt2712-mmc
22          - mediatek,mt6779-mmc
23          - mediatek,mt6795-mmc
24          - mediatek,mt7620-mmc
25          - mediatek,mt7622-mmc
26          - mediatek,mt8135-mmc
27          - mediatek,mt8173-mmc
28          - mediatek,mt8183-mmc
29          - mediatek,mt8516-mmc
30      - items:
31          - const: mediatek,mt7623-mmc
32          - const: mediatek,mt2701-mmc
33      - items:
34          - enum:
35              - mediatek,mt8186-mmc
36              - mediatek,mt8188-mmc
37              - mediatek,mt8192-mmc
38              - mediatek,mt8195-mmc
39          - const: mediatek,mt8183-mmc
40
41  reg:
42    minItems: 1
43    items:
44      - description: base register (required).
45      - description: top base register (required for MT8183).
46
47  clocks:
48    description:
49      Should contain phandle for the clock feeding the MMC controller.
50    minItems: 2
51    items:
52      - description: source clock (required).
53      - description: HCLK which used for host (required).
54      - description: independent source clock gate (required for MT2712).
55      - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
56      - description: msdc subsys clock gate (required for MT8192).
57      - description: peripheral bus clock gate (required for MT8192).
58      - description: AXI bus clock gate (required for MT8192).
59      - description: AHB bus clock gate (required for MT8192).
60
61  clock-names:
62    minItems: 2
63    items:
64      - const: source
65      - const: hclk
66      - const: source_cg
67      - const: bus_clk
68      - const: sys_cg
69      - const: pclk_cg
70      - const: axi_cg
71      - const: ahb_cg
72
73  interrupts:
74    description:
75      Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
76      interrupt is required and be configured as wakeup source irq.
77    minItems: 1
78    maxItems: 2
79
80  interrupt-names:
81    items:
82      - const: msdc
83      - const: sdio_wakeup
84
85  pinctrl-names:
86    description:
87      Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
88      will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
89      scenario.
90    minItems: 2
91    items:
92      - const: default
93      - const: state_uhs
94      - const: state_eint
95
96  pinctrl-0:
97    description:
98      should contain default/high speed pin ctrl.
99    maxItems: 1
100
101  pinctrl-1:
102    description:
103      should contain uhs mode pin ctrl.
104    maxItems: 1
105
106  pinctrl-2:
107    description:
108      should switch dat1 pin to GPIO mode.
109    maxItems: 1
110
111  assigned-clocks:
112    description:
113      PLL of the source clock.
114    maxItems: 1
115
116  assigned-clock-parents:
117    description:
118      parent of source clock, used for HS400 mode to get 400Mhz source clock.
119    maxItems: 1
120
121  hs400-ds-delay:
122    $ref: /schemas/types.yaml#/definitions/uint32
123    description:
124      HS400 DS delay setting.
125    minimum: 0
126    maximum: 0xffffffff
127
128  mediatek,hs200-cmd-int-delay:
129    $ref: /schemas/types.yaml#/definitions/uint32
130    description:
131      HS200 command internal delay setting.
132      This field has total 32 stages.
133      The value is an integer from 0 to 31.
134    minimum: 0
135    maximum: 31
136
137  mediatek,hs400-cmd-int-delay:
138    $ref: /schemas/types.yaml#/definitions/uint32
139    description:
140      HS400 command internal delay setting.
141      This field has total 32 stages.
142      The value is an integer from 0 to 31.
143    minimum: 0
144    maximum: 31
145
146  mediatek,hs400-cmd-resp-sel-rising:
147    $ref: /schemas/types.yaml#/definitions/flag
148    description:
149      HS400 command response sample selection.
150      If present, HS400 command responses are sampled on rising edges.
151      If not present, HS400 command responses are sampled on falling edges.
152
153  mediatek,hs400-ds-dly3:
154    $ref: /schemas/types.yaml#/definitions/uint32
155    description:
156      Gear of the third delay line for DS for input data latch in data
157      pad macro, there are 32 stages from 0 to 31.
158      For different corner IC, the time is different about one step, it is
159      about 100ps.
160      The value is confirmed by doing scan and calibration to find a best
161      value with corner IC and it is valid only for HS400 mode.
162    minimum: 0
163    maximum: 31
164
165  mediatek,latch-ck:
166    $ref: /schemas/types.yaml#/definitions/uint32
167    description:
168      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
169      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
170      if not present, default value is 0.
171      applied to compatible "mediatek,mt2701-mmc".
172    minimum: 0
173    maximum: 7
174
175  resets:
176    maxItems: 1
177
178  reset-names:
179    const: hrst
180
181required:
182  - compatible
183  - reg
184  - interrupts
185  - clocks
186  - clock-names
187  - pinctrl-names
188  - pinctrl-0
189  - pinctrl-1
190  - vmmc-supply
191  - vqmmc-supply
192
193if:
194  properties:
195    compatible:
196      contains:
197        const: mediatek,mt8183-mmc
198then:
199  properties:
200    reg:
201      minItems: 2
202
203unevaluatedProperties: false
204
205examples:
206  - |
207    #include <dt-bindings/interrupt-controller/irq.h>
208    #include <dt-bindings/interrupt-controller/arm-gic.h>
209    #include <dt-bindings/clock/mt8173-clk.h>
210    mmc0: mmc@11230000 {
211        compatible = "mediatek,mt8173-mmc";
212        reg = <0x11230000 0x1000>;
213        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
214        vmmc-supply = <&mt6397_vemc_3v3_reg>;
215        vqmmc-supply = <&mt6397_vio18_reg>;
216        clocks = <&pericfg CLK_PERI_MSDC30_0>,
217                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
218        clock-names = "source", "hclk";
219        pinctrl-names = "default", "state_uhs";
220        pinctrl-0 = <&mmc0_pins_default>;
221        pinctrl-1 = <&mmc0_pins_uhs>;
222        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
223        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
224        hs400-ds-delay = <0x14015>;
225        mediatek,hs200-cmd-int-delay = <26>;
226        mediatek,hs400-cmd-int-delay = <14>;
227        mediatek,hs400-cmd-resp-sel-rising;
228    };
229
230    mmc3: mmc@11260000 {
231        compatible = "mediatek,mt8173-mmc";
232        reg = <0x11260000 0x1000>;
233        clock-names = "source", "hclk";
234        clocks = <&pericfg CLK_PERI_MSDC30_3>,
235                 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
236        interrupt-names = "msdc", "sdio_wakeup";
237        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
238                     <&pio 23 IRQ_TYPE_LEVEL_LOW>;
239        pinctrl-names = "default", "state_uhs", "state_eint";
240        pinctrl-0 = <&mmc2_pins_default>;
241        pinctrl-1 = <&mmc2_pins_uhs>;
242        pinctrl-2 = <&mmc2_pins_eint>;
243        bus-width = <4>;
244        max-frequency = <200000000>;
245        cap-sd-highspeed;
246        sd-uhs-sdr104;
247        keep-power-in-suspend;
248        wakeup-source;
249        cap-sdio-irq;
250        no-mmc;
251        no-sd;
252        non-removable;
253        vmmc-supply = <&sdio_fixed_3v3>;
254        vqmmc-supply = <&mt6397_vgp3_reg>;
255        mmc-pwrseq = <&wifi_pwrseq>;
256    };
257
258...
259