1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas SDHI SD/MMC controller
8
9maintainers:
10  - Wolfram Sang <wsa+renesas@sang-engineering.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - const: renesas,sdhi-sh73a0  # R-Mobile APE6
17      - items:
18          - const: renesas,sdhi-r7s72100 # RZ/A1H
19      - items:
20          - const: renesas,sdhi-r7s9210 # SH-Mobile AG5
21      - items:
22          - const: renesas,sdhi-r8a73a4 # R-Mobile APE6
23      - items:
24          - const: renesas,sdhi-r8a7740 # R-Mobile A1
25      - items:
26          - enum:
27              - renesas,sdhi-r8a7778 # R-Car M1
28              - renesas,sdhi-r8a7779 # R-Car H1
29          - const: renesas,rcar-gen1-sdhi # R-Car Gen1
30      - items:
31          - enum:
32              - renesas,sdhi-r8a7742  # RZ/G1H
33              - renesas,sdhi-r8a7743  # RZ/G1M
34              - renesas,sdhi-r8a7744  # RZ/G1N
35              - renesas,sdhi-r8a7745  # RZ/G1E
36              - renesas,sdhi-r8a77470 # RZ/G1C
37              - renesas,sdhi-r8a7790  # R-Car H2
38              - renesas,sdhi-r8a7791  # R-Car M2-W
39              - renesas,sdhi-r8a7792  # R-Car V2H
40              - renesas,sdhi-r8a7793  # R-Car M2-N
41              - renesas,sdhi-r8a7794  # R-Car E2
42          - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
43      - items:
44          - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
45      - items:
46          - enum:
47              - renesas,sdhi-r8a774a1  # RZ/G2M
48              - renesas,sdhi-r8a774b1  # RZ/G2N
49              - renesas,sdhi-r8a774c0  # RZ/G2E
50              - renesas,sdhi-r8a774e1  # RZ/G2H
51              - renesas,sdhi-r8a7795   # R-Car H3
52              - renesas,sdhi-r8a7796   # R-Car M3-W
53              - renesas,sdhi-r8a77961  # R-Car M3-W+
54              - renesas,sdhi-r8a77965  # R-Car M3-N
55              - renesas,sdhi-r8a77970  # R-Car V3M
56              - renesas,sdhi-r8a77980  # R-Car V3H
57              - renesas,sdhi-r8a77990  # R-Car E3
58              - renesas,sdhi-r8a77995  # R-Car D3
59              - renesas,sdhi-r9a07g043 # RZ/G2UL and RZ/Five
60              - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
61              - renesas,sdhi-r9a07g054 # RZ/V2L
62              - renesas,sdhi-r9a08g045 # RZ/G3S
63              - renesas,sdhi-r9a09g011 # RZ/V2M
64          - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
65      - items:
66          - enum:
67              - renesas,sdhi-r8a779a0  # R-Car V3U
68              - renesas,sdhi-r8a779f0  # R-Car S4-8
69              - renesas,sdhi-r8a779g0  # R-Car V4H
70          - const: renesas,rcar-gen4-sdhi # R-Car Gen4
71
72  reg:
73    maxItems: 1
74
75  interrupts:
76    minItems: 1
77    maxItems: 3
78
79  clocks: true
80
81  clock-names: true
82
83  dmas:
84    minItems: 4
85    maxItems: 4
86
87  dma-names:
88    minItems: 4
89    maxItems: 4
90    items:
91      enum:
92        - tx
93        - rx
94
95  iommus:
96    maxItems: 1
97
98  power-domains:
99    maxItems: 1
100
101  resets:
102    maxItems: 1
103
104  pinctrl-0:
105    minItems: 1
106    maxItems: 2
107
108  pinctrl-1:
109    maxItems: 1
110
111  pinctrl-names: true
112
113  max-frequency: true
114
115allOf:
116  - $ref: mmc-controller.yaml
117
118  - if:
119      properties:
120        compatible:
121          contains:
122            enum:
123              - renesas,sdhi-r9a07g043
124              - renesas,sdhi-r9a07g044
125              - renesas,sdhi-r9a07g054
126              - renesas,sdhi-r9a08g045
127              - renesas,sdhi-r9a09g011
128    then:
129      properties:
130        clocks:
131          items:
132            - description: IMCLK, SDHI channel main clock1.
133            - description: CLK_HS, SDHI channel High speed clock which operates
134                           4 times that of SDHI channel main clock1.
135            - description: IMCLK2, SDHI channel main clock2. When this clock is
136                           turned off, external SD card detection cannot be
137                           detected.
138            - description: ACLK, SDHI channel bus clock.
139        clock-names:
140          items:
141            - const: core
142            - const: clkh
143            - const: cd
144            - const: aclk
145      required:
146        - clock-names
147        - resets
148    else:
149      if:
150        properties:
151          compatible:
152            contains:
153              enum:
154                - renesas,rcar-gen2-sdhi
155                - renesas,rcar-gen3-sdhi
156                - renesas,rcar-gen4-sdhi
157      then:
158        properties:
159          clocks:
160            minItems: 1
161            maxItems: 3
162          clock-names:
163            minItems: 1
164            uniqueItems: true
165            items:
166              - const: core
167              - enum: [ clkh, cd ]
168              - const: cd
169      else:
170        properties:
171          clocks:
172            minItems: 1
173            maxItems: 2
174          clock-names:
175            minItems: 1
176            items:
177              - const: core
178              - const: cd
179
180  - if:
181      properties:
182        compatible:
183          contains:
184            const: renesas,sdhi-mmc-r8a77470
185    then:
186      properties:
187        pinctrl-names:
188          items:
189            - const: state_uhs
190    else:
191      properties:
192        pinctrl-names:
193          minItems: 1
194          items:
195            - const: default
196            - const: state_uhs
197
198  - if:
199      properties:
200        compatible:
201          contains:
202            enum:
203              - renesas,sdhi-r7s72100
204              - renesas,sdhi-r7s9210
205    then:
206      required:
207        - clock-names
208      description:
209        The internal card detection logic that exists in these controllers is
210        sectioned off to be run by a separate second clock source to allow
211        the main core clock to be turned off to save power.
212
213required:
214  - compatible
215  - reg
216  - interrupts
217  - clocks
218  - power-domains
219
220unevaluatedProperties: false
221
222examples:
223  - |
224    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
225    #include <dt-bindings/interrupt-controller/arm-gic.h>
226    #include <dt-bindings/power/r8a7790-sysc.h>
227
228    sdhi0: mmc@ee100000 {
229            compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
230            reg = <0xee100000 0x328>;
231            interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
232            clocks = <&cpg CPG_MOD 314>;
233            dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
234            dma-names = "tx", "rx", "tx", "rx";
235            max-frequency = <195000000>;
236            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
237            resets = <&cpg 314>;
238    };
239
240    sdhi1: mmc@ee120000 {
241             compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
242             reg = <0xee120000 0x328>;
243             interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
244             clocks = <&cpg CPG_MOD 313>;
245             dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
246             dma-names = "tx", "rx", "tx", "rx";
247             max-frequency = <195000000>;
248             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
249             resets = <&cpg 313>;
250    };
251
252    sdhi2: mmc@ee140000 {
253             compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
254             reg = <0xee140000 0x100>;
255             interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
256             clocks = <&cpg CPG_MOD 312>;
257             dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
258             dma-names = "tx", "rx", "tx", "rx";
259             max-frequency = <97500000>;
260             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
261             resets = <&cpg 312>;
262     };
263
264     sdhi3: mmc@ee160000 {
265              compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
266              reg = <0xee160000 0x100>;
267              interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
268              clocks = <&cpg CPG_MOD 311>;
269              dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
270              dma-names = "tx", "rx", "tx", "rx";
271              max-frequency = <97500000>;
272              power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
273              resets = <&cpg 311>;
274    };
275