1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm SDHCI controller (sdhci-msm)
9
10maintainers:
11  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,msm8226-sdhci
27              - qcom,msm8953-sdhci
28              - qcom,msm8974-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33              - qcom,msm8998-sdhci
34          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35      - items:
36          - enum:
37              - qcom,qcs404-sdhci
38              - qcom,sc7180-sdhci
39              - qcom,sc7280-sdhci
40              - qcom,sdm630-sdhci
41              - qcom,sdm670-sdhci
42              - qcom,sdm845-sdhci
43              - qcom,sdx55-sdhci
44              - qcom,sdx65-sdhci
45              - qcom,sm6115-sdhci
46              - qcom,sm6125-sdhci
47              - qcom,sm6350-sdhci
48              - qcom,sm8150-sdhci
49              - qcom,sm8250-sdhci
50              - qcom,sm8450-sdhci
51          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
52
53  reg:
54    minItems: 1
55    maxItems: 4
56
57  reg-names:
58    minItems: 1
59    maxItems: 4
60
61  clocks:
62    minItems: 3
63    items:
64      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
65      - description: SDC MMC clock, MCLK
66      - description: TCXO clock
67      - description: clock for Inline Crypto Engine
68      - description: SDCC bus voter clock
69      - description: reference clock for RCLK delay calibration
70      - description: sleep clock for RCLK delay calibration
71
72  clock-names:
73    minItems: 2
74    items:
75      - const: iface
76      - const: core
77      - const: xo
78      - const: ice
79      - const: bus
80      - const: cal
81      - const: sleep
82
83  interrupts:
84    maxItems: 2
85
86  interrupt-names:
87    items:
88      - const: hc_irq
89      - const: pwr_irq
90
91  pinctrl-names:
92    minItems: 1
93    items:
94      - const: default
95      - const: sleep
96
97  pinctrl-0:
98    description:
99      Should specify pin control groups used for this controller.
100
101  pinctrl-1:
102    description:
103      Should specify sleep pin control groups used for this controller.
104
105  resets:
106    maxItems: 1
107
108  qcom,ddr-config:
109    $ref: /schemas/types.yaml#/definitions/uint32
110    description: platform specific settings for DDR_CONFIG reg.
111
112  qcom,dll-config:
113    $ref: /schemas/types.yaml#/definitions/uint32
114    description: platform specific settings for DLL_CONFIG reg.
115
116  iommus:
117    minItems: 1
118    maxItems: 8
119    description: |
120      phandle to apps_smmu node with sid mask.
121
122  interconnects:
123    items:
124      - description: data path, sdhc to ddr
125      - description: config path, cpu to sdhc
126
127  interconnect-names:
128    items:
129      - const: sdhc-ddr
130      - const: cpu-sdhc
131
132  power-domains:
133    description: A phandle to sdhci power domain node
134    maxItems: 1
135
136  mmc-ddr-1_8v: true
137
138  mmc-hs200-1_8v: true
139
140  mmc-hs400-1_8v: true
141
142  bus-width: true
143
144  max-frequency: true
145
146  operating-points-v2: true
147
148patternProperties:
149  '^opp-table(-[a-z0-9]+)?$':
150    if:
151      properties:
152        compatible:
153          const: operating-points-v2
154    then:
155      patternProperties:
156        '^opp-?[0-9]+$':
157          required:
158            - required-opps
159
160required:
161  - compatible
162  - reg
163  - clocks
164  - clock-names
165  - interrupts
166
167allOf:
168  - $ref: mmc-controller.yaml#
169
170  - if:
171      properties:
172        compatible:
173          contains:
174            enum:
175              - qcom,sdhci-msm-v4
176    then:
177      properties:
178        reg:
179          minItems: 2
180          items:
181            - description: Host controller register map
182            - description: SD Core register map
183            - description: CQE register map
184            - description: Inline Crypto Engine register map
185        reg-names:
186          minItems: 2
187          items:
188            - const: hc
189            - const: core
190            - const: cqhci
191            - const: ice
192    else:
193      properties:
194        reg:
195          minItems: 1
196          items:
197            - description: Host controller register map
198            - description: CQE register map
199            - description: Inline Crypto Engine register map
200        reg-names:
201          minItems: 1
202          items:
203            - const: hc
204            - const: cqhci
205            - const: ice
206
207unevaluatedProperties: false
208
209examples:
210  - |
211    #include <dt-bindings/interrupt-controller/arm-gic.h>
212    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
213    #include <dt-bindings/clock/qcom,rpmh.h>
214    #include <dt-bindings/power/qcom-rpmpd.h>
215
216    sdhc_2: mmc@8804000 {
217      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
218      reg = <0 0x08804000 0 0x1000>;
219
220      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
221                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
222      interrupt-names = "hc_irq", "pwr_irq";
223
224      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
225               <&gcc GCC_SDCC2_APPS_CLK>,
226               <&rpmhcc RPMH_CXO_CLK>;
227      clock-names = "iface", "core", "xo";
228      iommus = <&apps_smmu 0x4a0 0x0>;
229      qcom,dll-config = <0x0007642c>;
230      qcom,ddr-config = <0x80040868>;
231      power-domains = <&rpmhpd SM8250_CX>;
232
233      operating-points-v2 = <&sdhc2_opp_table>;
234
235      sdhc2_opp_table: opp-table {
236        compatible = "operating-points-v2";
237
238        opp-19200000 {
239          opp-hz = /bits/ 64 <19200000>;
240          required-opps = <&rpmhpd_opp_min_svs>;
241        };
242
243        opp-50000000 {
244          opp-hz = /bits/ 64 <50000000>;
245          required-opps = <&rpmhpd_opp_low_svs>;
246        };
247
248        opp-100000000 {
249          opp-hz = /bits/ 64 <100000000>;
250          required-opps = <&rpmhpd_opp_svs>;
251        };
252
253        opp-202000000 {
254          opp-hz = /bits/ 64 <202000000>;
255          required-opps = <&rpmhpd_opp_svs_l1>;
256        };
257      };
258    };
259