1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  Secure Digital Host Controller Interface (SDHCI) present on
14  Qualcomm SOCs supports SD/MMC/SDIO devices.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sdhci-msm-v4
21        deprecated: true
22      - items:
23          - enum:
24              - qcom,apq8084-sdhci
25              - qcom,msm8226-sdhci
26              - qcom,msm8953-sdhci
27              - qcom,msm8974-sdhci
28              - qcom,msm8976-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33              - qcom,msm8998-sdhci
34          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35      - items:
36          - enum:
37              - qcom,ipq5332-sdhci
38              - qcom,ipq9574-sdhci
39              - qcom,qcs404-sdhci
40              - qcom,sc7180-sdhci
41              - qcom,sc7280-sdhci
42              - qcom,sdm630-sdhci
43              - qcom,sdm670-sdhci
44              - qcom,sdm845-sdhci
45              - qcom,sdx55-sdhci
46              - qcom,sdx65-sdhci
47              - qcom,sm6115-sdhci
48              - qcom,sm6125-sdhci
49              - qcom,sm6350-sdhci
50              - qcom,sm6375-sdhci
51              - qcom,sm8150-sdhci
52              - qcom,sm8250-sdhci
53              - qcom,sm8350-sdhci
54              - qcom,sm8450-sdhci
55              - qcom,sm8550-sdhci
56          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
57
58  reg:
59    minItems: 1
60    maxItems: 4
61
62  reg-names:
63    minItems: 1
64    maxItems: 4
65
66  clocks:
67    minItems: 3
68    items:
69      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
70      - description: SDC MMC clock, MCLK
71      - description: TCXO clock
72      - description: clock for Inline Crypto Engine
73      - description: SDCC bus voter clock
74      - description: reference clock for RCLK delay calibration
75      - description: sleep clock for RCLK delay calibration
76
77  clock-names:
78    minItems: 2
79    items:
80      - const: iface
81      - const: core
82      - const: xo
83      - const: ice
84      - const: bus
85      - const: cal
86      - const: sleep
87
88  dma-coherent: true
89
90  interrupts:
91    maxItems: 2
92
93  interrupt-names:
94    items:
95      - const: hc_irq
96      - const: pwr_irq
97
98  pinctrl-names:
99    minItems: 1
100    items:
101      - const: default
102      - const: sleep
103
104  pinctrl-0:
105    description:
106      Should specify pin control groups used for this controller.
107
108  pinctrl-1:
109    description:
110      Should specify sleep pin control groups used for this controller.
111
112  resets:
113    maxItems: 1
114
115  qcom,ddr-config:
116    $ref: /schemas/types.yaml#/definitions/uint32
117    description: platform specific settings for DDR_CONFIG reg.
118
119  qcom,dll-config:
120    $ref: /schemas/types.yaml#/definitions/uint32
121    description: platform specific settings for DLL_CONFIG reg.
122
123  iommus:
124    minItems: 1
125    maxItems: 8
126    description: |
127      phandle to apps_smmu node with sid mask.
128
129  interconnects:
130    minItems: 1
131    items:
132      - description: data path, sdhc to ddr
133      - description: config path, cpu to sdhc
134
135  interconnect-names:
136    minItems: 1
137    items:
138      - const: sdhc-ddr
139      - const: cpu-sdhc
140
141  power-domains:
142    description: A phandle to sdhci power domain node
143    maxItems: 1
144
145  operating-points-v2: true
146
147patternProperties:
148  '^opp-table(-[a-z0-9]+)?$':
149    if:
150      properties:
151        compatible:
152          const: operating-points-v2
153    then:
154      patternProperties:
155        '^opp-?[0-9]+$':
156          required:
157            - required-opps
158
159required:
160  - compatible
161  - reg
162  - clocks
163  - clock-names
164  - interrupts
165
166allOf:
167  - $ref: sdhci-common.yaml#
168
169  - if:
170      properties:
171        compatible:
172          contains:
173            enum:
174              - qcom,sdhci-msm-v4
175    then:
176      properties:
177        reg:
178          minItems: 2
179          items:
180            - description: Host controller register map
181            - description: SD Core register map
182            - description: CQE register map
183            - description: Inline Crypto Engine register map
184        reg-names:
185          minItems: 2
186          items:
187            - const: hc
188            - const: core
189            - const: cqhci
190            - const: ice
191    else:
192      properties:
193        reg:
194          minItems: 1
195          items:
196            - description: Host controller register map
197            - description: CQE register map
198            - description: Inline Crypto Engine register map
199        reg-names:
200          minItems: 1
201          items:
202            - const: hc
203            - const: cqhci
204            - const: ice
205
206unevaluatedProperties: false
207
208examples:
209  - |
210    #include <dt-bindings/interrupt-controller/arm-gic.h>
211    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
212    #include <dt-bindings/clock/qcom,rpmh.h>
213    #include <dt-bindings/power/qcom-rpmpd.h>
214
215    sdhc_2: mmc@8804000 {
216      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
217      reg = <0 0x08804000 0 0x1000>;
218
219      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
220                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
221      interrupt-names = "hc_irq", "pwr_irq";
222
223      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
224               <&gcc GCC_SDCC2_APPS_CLK>,
225               <&rpmhcc RPMH_CXO_CLK>;
226      clock-names = "iface", "core", "xo";
227      iommus = <&apps_smmu 0x4a0 0x0>;
228      qcom,dll-config = <0x0007642c>;
229      qcom,ddr-config = <0x80040868>;
230      power-domains = <&rpmhpd SM8250_CX>;
231
232      operating-points-v2 = <&sdhc2_opp_table>;
233
234      sdhc2_opp_table: opp-table {
235        compatible = "operating-points-v2";
236
237        opp-19200000 {
238          opp-hz = /bits/ 64 <19200000>;
239          required-opps = <&rpmhpd_opp_min_svs>;
240        };
241
242        opp-50000000 {
243          opp-hz = /bits/ 64 <50000000>;
244          required-opps = <&rpmhpd_opp_low_svs>;
245        };
246
247        opp-100000000 {
248          opp-hz = /bits/ 64 <100000000>;
249          required-opps = <&rpmhpd_opp_svs>;
250        };
251
252        opp-202000000 {
253          opp-hz = /bits/ 64 <202000000>;
254          required-opps = <&rpmhpd_opp_svs_l1>;
255        };
256      };
257    };
258