1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Amlogic Meson DWMAC Ethernet controller
9
10maintainers:
11  - Neil Armstrong <narmstrong@baylibre.com>
12  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13
14# We need a select here so we don't match all nodes with 'snps,dwmac'
15select:
16  properties:
17    compatible:
18      contains:
19        enum:
20          - amlogic,meson6-dwmac
21          - amlogic,meson8b-dwmac
22          - amlogic,meson8m2-dwmac
23          - amlogic,meson-gxbb-dwmac
24          - amlogic,meson-axg-dwmac
25  required:
26    - compatible
27
28allOf:
29  - $ref: "snps,dwmac.yaml#"
30  - if:
31      properties:
32        compatible:
33          contains:
34            enum:
35              - amlogic,meson8b-dwmac
36              - amlogic,meson8m2-dwmac
37              - amlogic,meson-gxbb-dwmac
38              - amlogic,meson-axg-dwmac
39
40    then:
41      properties:
42        clocks:
43          items:
44            - description: GMAC main clock
45            - description: First parent clock of the internal mux
46            - description: Second parent clock of the internal mux
47
48        clock-names:
49          minItems: 3
50          maxItems: 3
51          items:
52            - const: stmmaceth
53            - const: clkin0
54            - const: clkin1
55
56        amlogic,tx-delay-ns:
57          $ref: /schemas/types.yaml#definitions/uint32
58          description:
59            The internal RGMII TX clock delay (provided by this driver) in
60            nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
61            When phy-mode is set to "rgmii" then the TX delay should be
62            explicitly configured. When not configured a fallback of 2ns is
63            used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
64            the TX clock delay is already provided by the PHY. In that case
65            this property should be set to 0ns (which disables the TX clock
66            delay in the MAC to prevent the clock from going off because both
67            PHY and MAC are adding a delay).
68            Any configuration is ignored when the phy-mode is set to "rmii".
69
70properties:
71  compatible:
72    additionalItems: true
73    maxItems: 3
74    items:
75      - enum:
76          - amlogic,meson6-dwmac
77          - amlogic,meson8b-dwmac
78          - amlogic,meson8m2-dwmac
79          - amlogic,meson-gxbb-dwmac
80          - amlogic,meson-axg-dwmac
81    contains:
82      enum:
83        - snps,dwmac-3.70a
84        - snps,dwmac
85
86  reg:
87    items:
88      - description:
89          The first register range should be the one of the DWMAC controller
90      - description:
91          The second range is is for the Amlogic specific configuration
92          (for example the PRG_ETHERNET register range on Meson8b and newer)
93
94required:
95  - compatible
96  - reg
97  - interrupts
98  - interrupt-names
99  - clocks
100  - clock-names
101  - phy-mode
102
103examples:
104  - |
105    ethmac: ethernet@c9410000 {
106         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
107         reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
108         interrupts = <8>;
109         interrupt-names = "macirq";
110         clocks = <&clk_eth>, <&clkc_fclk_div2>, <&clk_mpll2>;
111         clock-names = "stmmaceth", "clkin0", "clkin1";
112         phy-mode = "rgmii";
113    };
114