1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT7530 and MT7531 Ethernet Switches
8
9maintainers:
10  - Arınç ÜNAL <arinc.unal@arinc9.com>
11  - Landen Chao <Landen.Chao@mediatek.com>
12  - DENG Qingfang <dqfext@gmail.com>
13  - Sean Wang <sean.wang@mediatek.com>
14  - Daniel Golle <daniel@makrotopia.org>
15
16description: |
17  There are three versions of MT7530, standalone, in a multi-chip module and
18  built-into a SoC.
19
20  MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
21  MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs.
22
23  The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four
24  Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's
25  memory map rather than using MDIO. The switch got an internally connected 10G
26  CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs.
27
28  MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs
29  and the switch registers are directly mapped into SoC's memory map rather than
30  using MDIO. The DSA driver currently doesn't support MT7620 variants.
31
32  There is only the standalone version of MT7531.
33
34  Port 5 on MT7530 has got various ways of configuration:
35
36    - Port 5 can be used as a CPU port.
37
38    - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore,
39      the gmac of the SoC which is wired to port 5 can connect to the PHY.
40      This is usually used for connecting the wan port directly to the CPU to
41      achieve 2 Gbps routing in total.
42
43      The driver looks up the reg on the ethernet-phy node, which the phy-handle
44      property on the gmac node refers to, to mux the specified phy.
45
46      The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
47      compatible string and the reg must be 1. So, for now, only gmac1 of a
48      MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
49
50      For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
51
52      Check out example 5.
53
54    - For the multi-chip module MT7530, in case of an external phy wired to
55      gmac1 of the SoC, port 5 must not be enabled.
56
57      In case of muxing PHY 0 or 4, the external phy must not be enabled.
58
59      For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
60
61      Check out example 6.
62
63    - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port.
64
65      For the multi-chip module MT7530, the external phy must be wired TX to TX
66      to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired
67      this way.
68
69      For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the
70      external phy is connected TX to TX.
71
72      For the MT7621 SoCs, rgmii2 group must be claimed with gpio function.
73
74      Check out example 7.
75
76properties:
77  compatible:
78    oneOf:
79      - description:
80          Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC
81        const: mediatek,mt7530
82
83      - description:
84          Standalone MT7531
85        const: mediatek,mt7531
86
87      - description:
88          Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
89        const: mediatek,mt7621
90
91      - description:
92          Built-in switch of the MT7988 SoC
93        const: mediatek,mt7988-switch
94
95  reg:
96    maxItems: 1
97
98  core-supply:
99    description:
100      Phandle to the regulator node necessary for the core power.
101
102  "#gpio-cells":
103    const: 2
104
105  gpio-controller:
106    type: boolean
107    description: |
108      If defined, LED controller of the MT7530 switch will run on GPIO mode.
109
110      There are 15 controllable pins.
111      port 0 LED 0..2 as GPIO 0..2
112      port 1 LED 0..2 as GPIO 3..5
113      port 2 LED 0..2 as GPIO 6..8
114      port 3 LED 0..2 as GPIO 9..11
115      port 4 LED 0..2 as GPIO 12..14
116
117  "#interrupt-cells":
118    const: 1
119
120  interrupt-controller: true
121
122  interrupts:
123    maxItems: 1
124
125  io-supply:
126    description: |
127      Phandle to the regulator node necessary for the I/O power.
128      See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
129      details for the regulator setup on these boards.
130
131  mediatek,mcm:
132    type: boolean
133    description:
134      Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530
135      switch is a part of the multi-chip module.
136
137  reset-gpios:
138    description: |
139      GPIO to reset the switch. Use this if mediatek,mcm is not used.
140      This property is optional because some boards share the reset line with
141      other components which makes it impossible to probe the switch if the
142      reset line is used.
143    maxItems: 1
144
145  reset-names:
146    const: mcm
147
148  resets:
149    description:
150      Phandle pointing to the system reset controller with line index for the
151      ethsys.
152    maxItems: 1
153
154patternProperties:
155  "^(ethernet-)?ports$":
156    type: object
157    additionalProperties: true
158
159    patternProperties:
160      "^(ethernet-)?port@[0-6]$":
161        type: object
162        additionalProperties: true
163
164        properties:
165          reg:
166            description:
167              Port address described must be 5 or 6 for CPU port and from 0 to 5
168              for user ports.
169
170        allOf:
171          - if:
172              required: [ ethernet ]
173            then:
174              properties:
175                reg:
176                  enum:
177                    - 5
178                    - 6
179
180required:
181  - compatible
182  - reg
183
184$defs:
185  mt7530-dsa-port:
186    patternProperties:
187      "^(ethernet-)?ports$":
188        patternProperties:
189          "^(ethernet-)?port@[0-6]$":
190            if:
191              required: [ ethernet ]
192            then:
193              if:
194                properties:
195                  reg:
196                    const: 5
197              then:
198                properties:
199                  phy-mode:
200                    enum:
201                      - gmii
202                      - mii
203                      - rgmii
204              else:
205                properties:
206                  phy-mode:
207                    enum:
208                      - rgmii
209                      - trgmii
210
211  mt7531-dsa-port:
212    patternProperties:
213      "^(ethernet-)?ports$":
214        patternProperties:
215          "^(ethernet-)?port@[0-6]$":
216            if:
217              required: [ ethernet ]
218            then:
219              if:
220                properties:
221                  reg:
222                    const: 5
223              then:
224                properties:
225                  phy-mode:
226                    enum:
227                      - 1000base-x
228                      - 2500base-x
229                      - rgmii
230                      - sgmii
231              else:
232                properties:
233                  phy-mode:
234                    enum:
235                      - 1000base-x
236                      - 2500base-x
237                      - sgmii
238
239allOf:
240  - $ref: dsa.yaml#/$defs/ethernet-ports
241  - if:
242      required:
243        - mediatek,mcm
244    then:
245      properties:
246        reset-gpios: false
247
248      required:
249        - resets
250        - reset-names
251
252  - dependencies:
253      interrupt-controller: [ interrupts ]
254
255  - if:
256      properties:
257        compatible:
258          const: mediatek,mt7530
259    then:
260      $ref: "#/$defs/mt7530-dsa-port"
261      required:
262        - core-supply
263        - io-supply
264
265  - if:
266      properties:
267        compatible:
268          const: mediatek,mt7531
269    then:
270      $ref: "#/$defs/mt7531-dsa-port"
271      properties:
272        gpio-controller: false
273        mediatek,mcm: false
274
275  - if:
276      properties:
277        compatible:
278          const: mediatek,mt7621
279    then:
280      $ref: "#/$defs/mt7530-dsa-port"
281      required:
282        - mediatek,mcm
283
284  - if:
285      properties:
286        compatible:
287          const: mediatek,mt7988-switch
288    then:
289      $ref: "#/$defs/mt7530-dsa-port"
290      properties:
291        gpio-controller: false
292        mediatek,mcm: false
293        reset-names: false
294
295unevaluatedProperties: false
296
297examples:
298  # Example 1: Standalone MT7530
299  - |
300    #include <dt-bindings/gpio/gpio.h>
301
302    mdio {
303        #address-cells = <1>;
304        #size-cells = <0>;
305
306        switch@1f {
307            compatible = "mediatek,mt7530";
308            reg = <0x1f>;
309
310            reset-gpios = <&pio 33 0>;
311
312            core-supply = <&mt6323_vpa_reg>;
313            io-supply = <&mt6323_vemc3v3_reg>;
314
315            ethernet-ports {
316                #address-cells = <1>;
317                #size-cells = <0>;
318
319                port@0 {
320                    reg = <0>;
321                    label = "lan1";
322                };
323
324                port@1 {
325                    reg = <1>;
326                    label = "lan2";
327                };
328
329                port@2 {
330                    reg = <2>;
331                    label = "lan3";
332                };
333
334                port@3 {
335                    reg = <3>;
336                    label = "lan4";
337                };
338
339                port@4 {
340                    reg = <4>;
341                    label = "wan";
342                };
343
344                port@6 {
345                    reg = <6>;
346                    ethernet = <&gmac0>;
347                    phy-mode = "rgmii";
348
349                    fixed-link {
350                        speed = <1000>;
351                        full-duplex;
352                        pause;
353                    };
354                };
355            };
356        };
357    };
358
359  # Example 2: MT7530 in MT7623AI SoC
360  - |
361    #include <dt-bindings/reset/mt2701-resets.h>
362
363    mdio {
364        #address-cells = <1>;
365        #size-cells = <0>;
366
367        switch@1f {
368            compatible = "mediatek,mt7530";
369            reg = <0x1f>;
370
371            mediatek,mcm;
372            resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
373            reset-names = "mcm";
374
375            core-supply = <&mt6323_vpa_reg>;
376            io-supply = <&mt6323_vemc3v3_reg>;
377
378            ethernet-ports {
379                #address-cells = <1>;
380                #size-cells = <0>;
381
382                port@0 {
383                    reg = <0>;
384                    label = "lan1";
385                };
386
387                port@1 {
388                    reg = <1>;
389                    label = "lan2";
390                };
391
392                port@2 {
393                    reg = <2>;
394                    label = "lan3";
395                };
396
397                port@3 {
398                    reg = <3>;
399                    label = "lan4";
400                };
401
402                port@4 {
403                    reg = <4>;
404                    label = "wan";
405                };
406
407                port@6 {
408                    reg = <6>;
409                    ethernet = <&gmac0>;
410                    phy-mode = "trgmii";
411
412                    fixed-link {
413                        speed = <1000>;
414                        full-duplex;
415                        pause;
416                    };
417                };
418            };
419        };
420    };
421
422  # Example 3: Standalone MT7531
423  - |
424    #include <dt-bindings/gpio/gpio.h>
425    #include <dt-bindings/interrupt-controller/irq.h>
426
427    mdio {
428        #address-cells = <1>;
429        #size-cells = <0>;
430
431        switch@0 {
432            compatible = "mediatek,mt7531";
433            reg = <0>;
434
435            reset-gpios = <&pio 54 0>;
436
437            interrupt-controller;
438            #interrupt-cells = <1>;
439            interrupt-parent = <&pio>;
440            interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
441
442            ethernet-ports {
443                #address-cells = <1>;
444                #size-cells = <0>;
445
446                port@0 {
447                    reg = <0>;
448                    label = "lan1";
449                };
450
451                port@1 {
452                    reg = <1>;
453                    label = "lan2";
454                };
455
456                port@2 {
457                    reg = <2>;
458                    label = "lan3";
459                };
460
461                port@3 {
462                    reg = <3>;
463                    label = "lan4";
464                };
465
466                port@4 {
467                    reg = <4>;
468                    label = "wan";
469                };
470
471                port@6 {
472                    reg = <6>;
473                    ethernet = <&gmac0>;
474                    phy-mode = "2500base-x";
475
476                    fixed-link {
477                        speed = <2500>;
478                        full-duplex;
479                        pause;
480                    };
481                };
482            };
483        };
484    };
485
486  # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
487  - |
488    #include <dt-bindings/interrupt-controller/mips-gic.h>
489    #include <dt-bindings/reset/mt7621-reset.h>
490
491    mdio {
492        #address-cells = <1>;
493        #size-cells = <0>;
494
495        switch@1f {
496            compatible = "mediatek,mt7621";
497            reg = <0x1f>;
498
499            mediatek,mcm;
500            resets = <&sysc MT7621_RST_MCM>;
501            reset-names = "mcm";
502
503            interrupt-controller;
504            #interrupt-cells = <1>;
505            interrupt-parent = <&gic>;
506            interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
507
508            ethernet-ports {
509                #address-cells = <1>;
510                #size-cells = <0>;
511
512                port@0 {
513                    reg = <0>;
514                    label = "lan1";
515                };
516
517                port@1 {
518                    reg = <1>;
519                    label = "lan2";
520                };
521
522                port@2 {
523                    reg = <2>;
524                    label = "lan3";
525                };
526
527                port@3 {
528                    reg = <3>;
529                    label = "lan4";
530                };
531
532                port@4 {
533                    reg = <4>;
534                    label = "wan";
535                };
536
537                port@6 {
538                    reg = <6>;
539                    ethernet = <&gmac0>;
540                    phy-mode = "trgmii";
541
542                    fixed-link {
543                        speed = <1000>;
544                        full-duplex;
545                        pause;
546                    };
547                };
548            };
549        };
550    };
551
552  # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1
553  - |
554    #include <dt-bindings/interrupt-controller/mips-gic.h>
555    #include <dt-bindings/reset/mt7621-reset.h>
556
557    ethernet {
558        #address-cells = <1>;
559        #size-cells = <0>;
560
561        pinctrl-names = "default";
562        pinctrl-0 = <&rgmii2_pins>;
563
564        mac@1 {
565            compatible = "mediatek,eth-mac";
566            reg = <1>;
567
568            phy-mode = "rgmii";
569            phy-handle = <&example5_ethphy4>;
570        };
571
572        mdio {
573            #address-cells = <1>;
574            #size-cells = <0>;
575
576            /* MT7530's phy4 */
577            example5_ethphy4: ethernet-phy@4 {
578                reg = <4>;
579            };
580
581            switch@1f {
582                compatible = "mediatek,mt7621";
583                reg = <0x1f>;
584
585                mediatek,mcm;
586                resets = <&sysc MT7621_RST_MCM>;
587                reset-names = "mcm";
588
589                interrupt-controller;
590                #interrupt-cells = <1>;
591                interrupt-parent = <&gic>;
592                interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
593
594                ethernet-ports {
595                    #address-cells = <1>;
596                    #size-cells = <0>;
597
598                    port@0 {
599                        reg = <0>;
600                        label = "lan1";
601                    };
602
603                    port@1 {
604                        reg = <1>;
605                        label = "lan2";
606                    };
607
608                    port@2 {
609                        reg = <2>;
610                        label = "lan3";
611                    };
612
613                    port@3 {
614                        reg = <3>;
615                        label = "lan4";
616                    };
617
618                    /* Commented out, phy4 is connected to gmac1.
619                    port@4 {
620                        reg = <4>;
621                        label = "wan";
622                    };
623                    */
624
625                    port@6 {
626                        reg = <6>;
627                        ethernet = <&gmac0>;
628                        phy-mode = "trgmii";
629
630                        fixed-link {
631                            speed = <1000>;
632                            full-duplex;
633                            pause;
634                        };
635                    };
636                };
637            };
638        };
639    };
640
641  # Example 6: MT7621: mux external phy to SoC's gmac1
642  - |
643    #include <dt-bindings/interrupt-controller/mips-gic.h>
644    #include <dt-bindings/reset/mt7621-reset.h>
645
646    ethernet {
647        #address-cells = <1>;
648        #size-cells = <0>;
649
650        pinctrl-names = "default";
651        pinctrl-0 = <&rgmii2_pins>;
652
653        mac@1 {
654            compatible = "mediatek,eth-mac";
655            reg = <1>;
656
657            phy-mode = "rgmii";
658            phy-handle = <&example6_ethphy7>;
659        };
660
661        mdio {
662            #address-cells = <1>;
663            #size-cells = <0>;
664
665            /* External PHY */
666            example6_ethphy7: ethernet-phy@7 {
667                reg = <7>;
668                phy-mode = "rgmii";
669            };
670
671            switch@1f {
672                compatible = "mediatek,mt7621";
673                reg = <0x1f>;
674
675                mediatek,mcm;
676                resets = <&sysc MT7621_RST_MCM>;
677                reset-names = "mcm";
678
679                interrupt-controller;
680                #interrupt-cells = <1>;
681                interrupt-parent = <&gic>;
682                interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
683
684                ethernet-ports {
685                    #address-cells = <1>;
686                    #size-cells = <0>;
687
688                    port@0 {
689                        reg = <0>;
690                        label = "lan1";
691                    };
692
693                    port@1 {
694                        reg = <1>;
695                        label = "lan2";
696                    };
697
698                    port@2 {
699                        reg = <2>;
700                        label = "lan3";
701                    };
702
703                    port@3 {
704                        reg = <3>;
705                        label = "lan4";
706                    };
707
708                    port@4 {
709                        reg = <4>;
710                        label = "wan";
711                    };
712
713                    port@6 {
714                        reg = <6>;
715                        ethernet = <&gmac0>;
716                        phy-mode = "trgmii";
717
718                        fixed-link {
719                            speed = <1000>;
720                            full-duplex;
721                            pause;
722                        };
723                    };
724                };
725            };
726        };
727    };
728
729  # Example 7: MT7621: mux external phy to MT7530's port 5
730  - |
731    #include <dt-bindings/interrupt-controller/mips-gic.h>
732    #include <dt-bindings/reset/mt7621-reset.h>
733
734    ethernet {
735        #address-cells = <1>;
736        #size-cells = <0>;
737
738        pinctrl-names = "default";
739        pinctrl-0 = <&rgmii2_pins>;
740
741        mdio {
742            #address-cells = <1>;
743            #size-cells = <0>;
744
745            /* External PHY */
746            example7_ethphy7: ethernet-phy@7 {
747                reg = <7>;
748                phy-mode = "rgmii";
749            };
750
751            switch@1f {
752                compatible = "mediatek,mt7621";
753                reg = <0x1f>;
754
755                mediatek,mcm;
756                resets = <&sysc MT7621_RST_MCM>;
757                reset-names = "mcm";
758
759                interrupt-controller;
760                #interrupt-cells = <1>;
761                interrupt-parent = <&gic>;
762                interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
763
764                ethernet-ports {
765                    #address-cells = <1>;
766                    #size-cells = <0>;
767
768                    port@0 {
769                        reg = <0>;
770                        label = "lan1";
771                    };
772
773                    port@1 {
774                        reg = <1>;
775                        label = "lan2";
776                    };
777
778                    port@2 {
779                        reg = <2>;
780                        label = "lan3";
781                    };
782
783                    port@3 {
784                        reg = <3>;
785                        label = "lan4";
786                    };
787
788                    port@4 {
789                        reg = <4>;
790                        label = "wan";
791                    };
792
793                    port@5 {
794                        reg = <5>;
795                        label = "extphy";
796                        phy-mode = "rgmii-txid";
797                        phy-handle = <&example7_ethphy7>;
798                    };
799
800                    port@6 {
801                        reg = <6>;
802                        ethernet = <&gmac0>;
803                        phy-mode = "trgmii";
804
805                        fixed-link {
806                            speed = <1000>;
807                            full-duplex;
808                            pause;
809                        };
810                    };
811                };
812            };
813        };
814    };
815