1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros QCA83xx switch family
8
9maintainers:
10  - John Crispin <john@phrozen.org>
11
12description:
13  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14  describing a port needs to have a valid phandle referencing the internal PHY
15  it is connected to. This is because there is no N:N mapping of port and PHY
16  ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17  the switch node and declare the phandle for the port, referencing the internal
18  PHY it is connected to. In this config, an internal mdio-bus is registered and
19  the MDIO master is used for communication. Mixed external and internal
20  mdio-bus configurations are not supported by the hardware.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - qca,qca8327
27          - qca,qca8328
28          - qca,qca8334
29          - qca,qca8337
30    description: |
31      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
32      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
33      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
34      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
35
36  reg:
37    maxItems: 1
38
39  reset-gpios:
40    description:
41      GPIO to be used to reset the whole device
42    maxItems: 1
43
44  qca,ignore-power-on-sel:
45    $ref: /schemas/types.yaml#/definitions/flag
46    description:
47      Ignore power-on pin strapping to configure LED open-drain or EEPROM
48      presence. This is needed for devices with incorrect configuration or when
49      the OEM has decided not to use pin strapping and falls back to SW regs.
50
51  qca,led-open-drain:
52    $ref: /schemas/types.yaml#/definitions/flag
53    description:
54      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
55      be set, otherwise the driver will fail at probe. This is required if the
56      OEM does not use pin strapping to set this mode and prefers to set it
57      using SW regs. The pin strappings related to LED open-drain mode are
58      B68 on the QCA832x and B49 on the QCA833x.
59
60  mdio:
61    $ref: /schemas/net/mdio.yaml#
62    unevaluatedProperties: false
63    description: Qca8k switch have an internal mdio to access switch port.
64                 If this is not present, the legacy mapping is used and the
65                 internal mdio access is used.
66                 With the legacy mapping the reg corresponding to the internal
67                 mdio is the switch reg with an offset of -1.
68
69patternProperties:
70  "^(ethernet-)?ports$":
71    type: object
72    properties:
73      '#address-cells':
74        const: 1
75      '#size-cells':
76        const: 0
77
78    patternProperties:
79      "^(ethernet-)?port@[0-6]$":
80        type: object
81        description: Ethernet switch ports
82
83        $ref: dsa-port.yaml#
84
85        properties:
86          qca,sgmii-rxclk-falling-edge:
87            $ref: /schemas/types.yaml#/definitions/flag
88            description:
89              Set the receive clock phase to falling edge. Mostly commonly used on
90              the QCA8327 with CPU port 0 set to SGMII.
91
92          qca,sgmii-txclk-falling-edge:
93            $ref: /schemas/types.yaml#/definitions/flag
94            description:
95              Set the transmit clock phase to falling edge.
96
97          qca,sgmii-enable-pll:
98            $ref: /schemas/types.yaml#/definitions/flag
99            description:
100              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
101              Signal Detection. On the QCA8327 this should not be enabled, otherwise
102              the SGMII port will not initialize. When used on the QCA8337, revision 3
103              or greater, a warning will be displayed. When the CPU port is set to
104              SGMII on the QCA8337, it is advised to set this unless a communication
105              issue is observed.
106
107        unevaluatedProperties: false
108
109oneOf:
110  - required:
111      - ports
112  - required:
113      - ethernet-ports
114
115required:
116  - compatible
117  - reg
118
119additionalProperties: true
120
121examples:
122  - |
123    #include <dt-bindings/gpio/gpio.h>
124
125    mdio {
126        #address-cells = <1>;
127        #size-cells = <0>;
128
129        external_phy_port1: ethernet-phy@0 {
130            reg = <0>;
131        };
132
133        external_phy_port2: ethernet-phy@1 {
134            reg = <1>;
135        };
136
137        external_phy_port3: ethernet-phy@2 {
138            reg = <2>;
139        };
140
141        external_phy_port4: ethernet-phy@3 {
142            reg = <3>;
143        };
144
145        external_phy_port5: ethernet-phy@4 {
146            reg = <4>;
147        };
148
149        switch@10 {
150            compatible = "qca,qca8337";
151            #address-cells = <1>;
152            #size-cells = <0>;
153            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
154            reg = <0x10>;
155
156            ports {
157                #address-cells = <1>;
158                #size-cells = <0>;
159
160                port@0 {
161                    reg = <0>;
162                    ethernet = <&gmac1>;
163                    phy-mode = "rgmii";
164
165                    fixed-link {
166                        speed = <1000>;
167                        full-duplex;
168                    };
169                };
170
171                port@1 {
172                    reg = <1>;
173                    label = "lan1";
174                    phy-handle = <&external_phy_port1>;
175                };
176
177                port@2 {
178                    reg = <2>;
179                    label = "lan2";
180                    phy-handle = <&external_phy_port2>;
181                };
182
183                port@3 {
184                    reg = <3>;
185                    label = "lan3";
186                    phy-handle = <&external_phy_port3>;
187                };
188
189                port@4 {
190                    reg = <4>;
191                    label = "lan4";
192                    phy-handle = <&external_phy_port4>;
193                };
194
195                port@5 {
196                    reg = <5>;
197                    label = "wan";
198                    phy-handle = <&external_phy_port5>;
199                };
200            };
201        };
202    };
203  - |
204    #include <dt-bindings/gpio/gpio.h>
205
206    mdio {
207        #address-cells = <1>;
208        #size-cells = <0>;
209
210        switch@10 {
211            compatible = "qca,qca8337";
212            #address-cells = <1>;
213            #size-cells = <0>;
214            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
215            reg = <0x10>;
216
217            ports {
218                #address-cells = <1>;
219                #size-cells = <0>;
220
221                port@0 {
222                    reg = <0>;
223                    ethernet = <&gmac1>;
224                    phy-mode = "rgmii";
225
226                    fixed-link {
227                        speed = <1000>;
228                        full-duplex;
229                    };
230                };
231
232                port@1 {
233                    reg = <1>;
234                    label = "lan1";
235                    phy-mode = "internal";
236                    phy-handle = <&internal_phy_port1>;
237                };
238
239                port@2 {
240                    reg = <2>;
241                    label = "lan2";
242                    phy-mode = "internal";
243                    phy-handle = <&internal_phy_port2>;
244                };
245
246                port@3 {
247                    reg = <3>;
248                    label = "lan3";
249                    phy-mode = "internal";
250                    phy-handle = <&internal_phy_port3>;
251                };
252
253                port@4 {
254                    reg = <4>;
255                    label = "lan4";
256                    phy-mode = "internal";
257                    phy-handle = <&internal_phy_port4>;
258                };
259
260                port@5 {
261                    reg = <5>;
262                    label = "wan";
263                    phy-mode = "internal";
264                    phy-handle = <&internal_phy_port5>;
265                };
266
267                port@6 {
268                    reg = <0>;
269                    ethernet = <&gmac1>;
270                    phy-mode = "sgmii";
271
272                    qca,sgmii-rxclk-falling-edge;
273
274                    fixed-link {
275                        speed = <1000>;
276                        full-duplex;
277                    };
278                };
279            };
280
281            mdio {
282                #address-cells = <1>;
283                #size-cells = <0>;
284
285                internal_phy_port1: ethernet-phy@0 {
286                    reg = <0>;
287                };
288
289                internal_phy_port2: ethernet-phy@1 {
290                    reg = <1>;
291                };
292
293                internal_phy_port3: ethernet-phy@2 {
294                    reg = <2>;
295                };
296
297                internal_phy_port4: ethernet-phy@3 {
298                    reg = <3>;
299                };
300
301                internal_phy_port5: ethernet-phy@4 {
302                    reg = <4>;
303                };
304            };
305        };
306    };
307