1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. NVMEM OPP bindings
8
9maintainers:
10  - Ilia Lin <ilia.lin@kernel.org>
11
12allOf:
13  - $ref: opp-v2-base.yaml#
14
15description: |
16  In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
17  the CPU frequencies subset and voltage value of each OPP varies based on
18  the silicon variant in use.
19  Qualcomm Technologies, Inc. Process Voltage Scaling Tables
20  defines the voltage and frequency value based on the speedbin blown in
21  the efuse combination.
22  The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23  the OPP framework with required information (existing HW bitmap).
24  This is used to determine the voltage and frequency value for each OPP of
25  operating-points-v2 table when it is parsed by the OPP framework.
26
27properties:
28  compatible:
29    const: operating-points-v2-kryo-cpu
30
31  nvmem-cells:
32    description: |
33      A phandle pointing to a nvmem-cells node representing the
34      efuse registers that has information about the
35      speedbin that is used to select the right frequency/voltage
36      value pair.
37
38  opp-shared: true
39
40patternProperties:
41  '^opp-?[0-9]+$':
42    type: object
43
44    properties:
45      opp-hz: true
46
47      opp-microvolt: true
48
49      opp-supported-hw:
50        description: |
51          A single 32 bit bitmap value, representing compatible HW.
52          Bitmap:
53          0:  MSM8996, speedbin 0
54          1:  MSM8996, speedbin 1
55          2:  MSM8996, speedbin 2
56          3-31:  unused
57        maximum: 0x7
58
59      clock-latency-ns: true
60
61      required-opps: true
62
63    required:
64      - opp-hz
65
66required:
67  - compatible
68
69if:
70  required:
71    - nvmem-cells
72then:
73  patternProperties:
74    '^opp-?[0-9]+$':
75      required:
76        - opp-supported-hw
77
78additionalProperties: false
79
80examples:
81  - |
82    / {
83        model = "Qualcomm Technologies, Inc. DB820c";
84        compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
85        #address-cells = <2>;
86        #size-cells = <2>;
87
88        cpus {
89            #address-cells = <2>;
90            #size-cells = <0>;
91
92            CPU0: cpu@0 {
93                device_type = "cpu";
94                compatible = "qcom,kryo";
95                reg = <0x0 0x0>;
96                enable-method = "psci";
97                cpu-idle-states = <&CPU_SLEEP_0>;
98                capacity-dmips-mhz = <1024>;
99                clocks = <&kryocc 0>;
100                operating-points-v2 = <&cluster0_opp>;
101                #cooling-cells = <2>;
102                next-level-cache = <&L2_0>;
103                L2_0: l2-cache {
104                    compatible = "cache";
105                    cache-level = <2>;
106                };
107            };
108
109            CPU1: cpu@1 {
110                device_type = "cpu";
111                compatible = "qcom,kryo";
112                reg = <0x0 0x1>;
113                enable-method = "psci";
114                cpu-idle-states = <&CPU_SLEEP_0>;
115                capacity-dmips-mhz = <1024>;
116                clocks = <&kryocc 0>;
117                operating-points-v2 = <&cluster0_opp>;
118                #cooling-cells = <2>;
119                next-level-cache = <&L2_0>;
120            };
121
122            CPU2: cpu@100 {
123                device_type = "cpu";
124                compatible = "qcom,kryo";
125                reg = <0x0 0x100>;
126                enable-method = "psci";
127                cpu-idle-states = <&CPU_SLEEP_0>;
128                capacity-dmips-mhz = <1024>;
129                clocks = <&kryocc 1>;
130                operating-points-v2 = <&cluster1_opp>;
131                #cooling-cells = <2>;
132                next-level-cache = <&L2_1>;
133                L2_1: l2-cache {
134                    compatible = "cache";
135                    cache-level = <2>;
136                };
137            };
138
139            CPU3: cpu@101 {
140                device_type = "cpu";
141                compatible = "qcom,kryo";
142                reg = <0x0 0x101>;
143                enable-method = "psci";
144                cpu-idle-states = <&CPU_SLEEP_0>;
145                capacity-dmips-mhz = <1024>;
146                clocks = <&kryocc 1>;
147                operating-points-v2 = <&cluster1_opp>;
148                #cooling-cells = <2>;
149                next-level-cache = <&L2_1>;
150            };
151
152            cpu-map {
153                cluster0 {
154                    core0 {
155                        cpu = <&CPU0>;
156                    };
157
158                    core1 {
159                        cpu = <&CPU1>;
160                    };
161                };
162
163                cluster1 {
164                    core0 {
165                        cpu = <&CPU2>;
166                    };
167
168                    core1 {
169                        cpu = <&CPU3>;
170                    };
171                };
172            };
173        };
174
175        cluster0_opp: opp-table-0 {
176            compatible = "operating-points-v2-kryo-cpu";
177            nvmem-cells = <&speedbin_efuse>;
178            opp-shared;
179
180            opp-307200000 {
181                opp-hz = /bits/ 64 <307200000>;
182                opp-microvolt = <905000 905000 1140000>;
183                opp-supported-hw = <0x7>;
184                clock-latency-ns = <200000>;
185            };
186            opp-1401600000 {
187                opp-hz = /bits/ 64 <1401600000>;
188                opp-microvolt = <1140000 905000 1140000>;
189                opp-supported-hw = <0x5>;
190                clock-latency-ns = <200000>;
191            };
192            opp-1593600000 {
193                opp-hz = /bits/ 64 <1593600000>;
194                opp-microvolt = <1140000 905000 1140000>;
195                opp-supported-hw = <0x1>;
196                clock-latency-ns = <200000>;
197            };
198        };
199
200        cluster1_opp: opp-table-1 {
201            compatible = "operating-points-v2-kryo-cpu";
202            nvmem-cells = <&speedbin_efuse>;
203            opp-shared;
204
205            opp-307200000 {
206                opp-hz = /bits/ 64 <307200000>;
207                opp-microvolt = <905000 905000 1140000>;
208                opp-supported-hw = <0x7>;
209                clock-latency-ns = <200000>;
210            };
211            opp-1804800000 {
212                opp-hz = /bits/ 64 <1804800000>;
213                opp-microvolt = <1140000 905000 1140000>;
214                opp-supported-hw = <0x6>;
215                clock-latency-ns = <200000>;
216            };
217            opp-1900800000 {
218                opp-hz = /bits/ 64 <1900800000>;
219                opp-microvolt = <1140000 905000 1140000>;
220                opp-supported-hw = <0x4>;
221                clock-latency-ns = <200000>;
222            };
223            opp-2150400000 {
224                opp-hz = /bits/ 64 <2150400000>;
225                opp-microvolt = <1140000 905000 1140000>;
226                opp-supported-hw = <0x1>;
227                clock-latency-ns = <200000>;
228            };
229        };
230
231        smem {
232            compatible = "qcom,smem";
233            memory-region = <&smem_mem>;
234            hwlocks = <&tcsr_mutex 3>;
235        };
236
237        soc {
238            #address-cells = <1>;
239            #size-cells = <1>;
240
241            qfprom: qfprom@74000 {
242                compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
243                reg = <0x00074000 0x8ff>;
244                #address-cells = <1>;
245                #size-cells = <1>;
246
247                speedbin_efuse: speedbin@133 {
248                    reg = <0x133 0x1>;
249                    bits = <5 3>;
250                };
251            };
252        };
253    };
254