1* Mobiveil AXI PCIe Root Port Bridge DT description
2
3Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
4has up to 8 outbound and inbound windows for the address translation.
5
6Required properties:
7- #address-cells: Address representation for root ports, set to <3>
8- #size-cells: Size representation for root ports, set to <2>
9- #interrupt-cells: specifies the number of cells needed to encode an
10	interrupt source. The value must be 1.
11- compatible: Should contain "mbvl,gpex40-pcie"
12- reg: Should contain PCIe registers location and length
13	Mandatory:
14	"config_axi_slave": PCIe controller registers
15	"csr_axi_slave"	  : Bridge config registers
16	Optional:
17	"gpio_slave"	  : GPIO registers to control slot power
18	"apb_csr"	  : MSI registers
19
20- device_type: must be "pci"
21- apio-wins : number of requested apio outbound windows
22		default 2 outbound windows are configured -
23		1. Config window
24		2. Memory window
25- ppio-wins : number of requested ppio inbound windows
26		default 1 inbound memory window is configured.
27- bus-range: PCI bus numbers covered
28- interrupt-controller: identifies the node as an interrupt controller
29- #interrupt-cells: specifies the number of cells needed to encode an
30	interrupt source. The value must be 1.
31- interrupts: The interrupt line of the PCIe controller
32		last cell of this field is set to 4 to
33		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
34- interrupt-map-mask,
35	interrupt-map: standard PCI properties to define the mapping of the
36	PCI interface to interrupt numbers.
37- ranges: ranges for the PCI memory regions (I/O space region is not
38	supported by hardware)
39	Please refer to the standard PCI bus binding document for a more
40	detailed explanation
41
42
43Example:
44++++++++
45	pcie0: pcie@a0000000 {
46		#address-cells = <3>;
47		#size-cells = <2>;
48		compatible = "mbvl,gpex40-pcie";
49		reg =	<0xa0000000 0x00001000>,
50			<0xb0000000 0x00010000>,
51			<0xff000000 0x00200000>,
52			<0xb0010000 0x00001000>;
53		reg-names =	"config_axi_slave",
54				"csr_axi_slave",
55				"gpio_slave",
56				"apb_csr";
57		device_type = "pci";
58		apio-wins = <2>;
59		ppio-wins = <1>;
60		bus-range = <0x00000000 0x000000ff>;
61		interrupt-controller;
62		interrupt-parent = <&gic>;
63		#interrupt-cells = <1>;
64		interrupts = < 0 89 4 >;
65		interrupt-map-mask = <0 0 0 7>;
66		interrupt-map = <0 0 0 0 &pci_express 0>,
67				<0 0 0 1 &pci_express 1>,
68				<0 0 0 2 &pci_express 2>,
69				<0 0 0 3 &pci_express 3>;
70		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
71
72	};
73