1e4dffb67SVidya Sagar# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2e4dffb67SVidya Sagar%YAML 1.2 3e4dffb67SVidya Sagar--- 4e4dffb67SVidya Sagar$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# 5e4dffb67SVidya Sagar$schema: http://devicetree.org/meta-schemas/core.yaml# 6e4dffb67SVidya Sagar 7e4dffb67SVidya Sagartitle: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based) 8e4dffb67SVidya Sagar 9e4dffb67SVidya Sagarmaintainers: 10e4dffb67SVidya Sagar - Thierry Reding <thierry.reding@gmail.com> 11e4dffb67SVidya Sagar - Jon Hunter <jonathanh@nvidia.com> 12e4dffb67SVidya Sagar - Vidya Sagar <vidyas@nvidia.com> 13e4dffb67SVidya Sagar 14e4dffb67SVidya Sagardescription: | 15e4dffb67SVidya Sagar This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16e4dffb67SVidya Sagar inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some 17e4dffb67SVidya Sagar of the controller instances are dual mode; they can work either in Root 18e4dffb67SVidya Sagar Port mode or Endpoint mode but one at a time. 19e4dffb67SVidya Sagar 20e4dffb67SVidya Sagar On Tegra194, controllers C0, C4 and C5 support Endpoint mode. 21*b949e466SVidya Sagar On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode. 22e4dffb67SVidya Sagar 23e4dffb67SVidya Sagar Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 24e4dffb67SVidya Sagar operate in the Endpoint mode because of the way the platform is designed. 25e4dffb67SVidya Sagar 26e4dffb67SVidya Sagarproperties: 27e4dffb67SVidya Sagar compatible: 28e4dffb67SVidya Sagar enum: 29e4dffb67SVidya Sagar - nvidia,tegra194-pcie-ep 30*b949e466SVidya Sagar - nvidia,tegra234-pcie-ep 31e4dffb67SVidya Sagar 32e4dffb67SVidya Sagar reg: 33e4dffb67SVidya Sagar items: 34e4dffb67SVidya Sagar - description: controller's application logic registers 35e4dffb67SVidya Sagar - description: iATU and DMA registers. This is where the iATU (internal 36e4dffb67SVidya Sagar Address Translation Unit) registers of the PCIe core are made 37e4dffb67SVidya Sagar available for software access. 38e4dffb67SVidya Sagar - description: aperture where the Root Port's own configuration 39e4dffb67SVidya Sagar registers are available. 40e4dffb67SVidya Sagar - description: aperture used to map the remote Root Complex address space 41e4dffb67SVidya Sagar 42e4dffb67SVidya Sagar reg-names: 43e4dffb67SVidya Sagar items: 44e4dffb67SVidya Sagar - const: appl 45e4dffb67SVidya Sagar - const: atu_dma 46e4dffb67SVidya Sagar - const: dbi 47e4dffb67SVidya Sagar - const: addr_space 48e4dffb67SVidya Sagar 49e4dffb67SVidya Sagar interrupts: 50e4dffb67SVidya Sagar items: 51e4dffb67SVidya Sagar - description: controller interrupt 52e4dffb67SVidya Sagar 53e4dffb67SVidya Sagar interrupt-names: 54e4dffb67SVidya Sagar items: 55e4dffb67SVidya Sagar - const: intr 56e4dffb67SVidya Sagar 57e4dffb67SVidya Sagar clocks: 58e4dffb67SVidya Sagar items: 59e4dffb67SVidya Sagar - description: module clock 60e4dffb67SVidya Sagar 61e4dffb67SVidya Sagar clock-names: 62e4dffb67SVidya Sagar items: 63e4dffb67SVidya Sagar - const: core 64e4dffb67SVidya Sagar 65e4dffb67SVidya Sagar resets: 66e4dffb67SVidya Sagar items: 67e4dffb67SVidya Sagar - description: APB bus interface reset 68e4dffb67SVidya Sagar - description: module reset 69e4dffb67SVidya Sagar 70e4dffb67SVidya Sagar reset-names: 71e4dffb67SVidya Sagar items: 72e4dffb67SVidya Sagar - const: apb 73e4dffb67SVidya Sagar - const: core 74e4dffb67SVidya Sagar 75e4dffb67SVidya Sagar reset-gpios: 76e4dffb67SVidya Sagar description: Must contain a phandle to a GPIO controller followed by GPIO 77e4dffb67SVidya Sagar that is being used as PERST input signal. Please refer to pci.txt. 78e4dffb67SVidya Sagar 79e4dffb67SVidya Sagar phys: 80e4dffb67SVidya Sagar minItems: 1 81e4dffb67SVidya Sagar maxItems: 8 82e4dffb67SVidya Sagar 83e4dffb67SVidya Sagar phy-names: 84e4dffb67SVidya Sagar minItems: 1 85e4dffb67SVidya Sagar items: 86e4dffb67SVidya Sagar - const: p2u-0 87e4dffb67SVidya Sagar - const: p2u-1 88e4dffb67SVidya Sagar - const: p2u-2 89e4dffb67SVidya Sagar - const: p2u-3 90e4dffb67SVidya Sagar - const: p2u-4 91e4dffb67SVidya Sagar - const: p2u-5 92e4dffb67SVidya Sagar - const: p2u-6 93e4dffb67SVidya Sagar - const: p2u-7 94e4dffb67SVidya Sagar 95e4dffb67SVidya Sagar power-domains: 96e4dffb67SVidya Sagar maxItems: 1 97e4dffb67SVidya Sagar description: | 98e4dffb67SVidya Sagar A phandle to the node that controls power to the respective PCIe 99e4dffb67SVidya Sagar controller and a specifier name for the PCIe controller. 100e4dffb67SVidya Sagar 101*b949e466SVidya Sagar Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" 102*b949e466SVidya Sagar Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" 103e4dffb67SVidya Sagar 104e4dffb67SVidya Sagar interconnects: 105e4dffb67SVidya Sagar items: 106e4dffb67SVidya Sagar - description: memory read client 107e4dffb67SVidya Sagar - description: memory write client 108e4dffb67SVidya Sagar 109e4dffb67SVidya Sagar interconnect-names: 110e4dffb67SVidya Sagar items: 111e4dffb67SVidya Sagar - const: dma-mem # read 112e4dffb67SVidya Sagar - const: write 113e4dffb67SVidya Sagar 114e4dffb67SVidya Sagar dma-coherent: true 115e4dffb67SVidya Sagar 116e4dffb67SVidya Sagar nvidia,bpmp: 117e4dffb67SVidya Sagar $ref: /schemas/types.yaml#/definitions/phandle-array 118e4dffb67SVidya Sagar description: | 119e4dffb67SVidya Sagar Must contain a pair of phandles to BPMP controller node followed by 120e4dffb67SVidya Sagar controller ID. Following are the controller IDs for each controller: 121e4dffb67SVidya Sagar 122*b949e466SVidya Sagar Tegra194 123*b949e466SVidya Sagar 124e4dffb67SVidya Sagar 0: C0 125e4dffb67SVidya Sagar 1: C1 126e4dffb67SVidya Sagar 2: C2 127e4dffb67SVidya Sagar 3: C3 128e4dffb67SVidya Sagar 4: C4 129e4dffb67SVidya Sagar 5: C5 130*b949e466SVidya Sagar 131*b949e466SVidya Sagar Tegra234 132*b949e466SVidya Sagar 133*b949e466SVidya Sagar 0 : C0 134*b949e466SVidya Sagar 1 : C1 135*b949e466SVidya Sagar 2 : C2 136*b949e466SVidya Sagar 3 : C3 137*b949e466SVidya Sagar 4 : C4 138*b949e466SVidya Sagar 5 : C5 139*b949e466SVidya Sagar 6 : C6 140*b949e466SVidya Sagar 7 : C7 141*b949e466SVidya Sagar 8 : C8 142*b949e466SVidya Sagar 9 : C9 143*b949e466SVidya Sagar 10: C10 144*b949e466SVidya Sagar 145e4dffb67SVidya Sagar items: 146e4dffb67SVidya Sagar - items: 147e4dffb67SVidya Sagar - description: phandle to BPMP controller node 148e4dffb67SVidya Sagar - description: PCIe controller ID 149*b949e466SVidya Sagar maximum: 10 150e4dffb67SVidya Sagar 151e4dffb67SVidya Sagar nvidia,aspm-cmrt-us: 152e4dffb67SVidya Sagar description: Common Mode Restore Time for proper operation of ASPM to be 153e4dffb67SVidya Sagar specified in microseconds 154e4dffb67SVidya Sagar 155e4dffb67SVidya Sagar nvidia,aspm-pwr-on-t-us: 156e4dffb67SVidya Sagar description: Power On time for proper operation of ASPM to be specified in 157e4dffb67SVidya Sagar microseconds 158e4dffb67SVidya Sagar 159e4dffb67SVidya Sagar nvidia,aspm-l0s-entrance-latency-us: 160e4dffb67SVidya Sagar description: ASPM L0s entrance latency to be specified in microseconds 161e4dffb67SVidya Sagar 162e4dffb67SVidya Sagar vddio-pex-ctl-supply: 163e4dffb67SVidya Sagar description: A phandle to the regulator supply for PCIe side band signals 164e4dffb67SVidya Sagar 165e4dffb67SVidya Sagar nvidia,refclk-select-gpios: 166e4dffb67SVidya Sagar maxItems: 1 167e4dffb67SVidya Sagar description: GPIO used to enable REFCLK to controller from the host 168e4dffb67SVidya Sagar 169*b949e466SVidya Sagar nvidia,enable-ext-refclk: 170*b949e466SVidya Sagar description: | 171*b949e466SVidya Sagar This boolean property needs to be present if the controller is configured 172*b949e466SVidya Sagar to receive Reference Clock from the host. 173*b949e466SVidya Sagar NOTE: This is applicable only for Tegra234. 174*b949e466SVidya Sagar 175*b949e466SVidya Sagar $ref: /schemas/types.yaml#/definitions/flag 176*b949e466SVidya Sagar 177*b949e466SVidya Sagar nvidia,enable-srns: 178*b949e466SVidya Sagar description: | 179*b949e466SVidya Sagar This boolean property needs to be present if the controller is 180*b949e466SVidya Sagar configured to operate in SRNS (Separate Reference Clocks with No 181*b949e466SVidya Sagar Spread-Spectrum Clocking). NOTE: This is applicable only for 182*b949e466SVidya Sagar Tegra234. 183*b949e466SVidya Sagar 184*b949e466SVidya Sagar $ref: /schemas/types.yaml#/definitions/flag 185*b949e466SVidya Sagar 186e4dffb67SVidya SagarallOf: 187e4dffb67SVidya Sagar - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# 188e4dffb67SVidya Sagar 189e4dffb67SVidya SagarunevaluatedProperties: false 190e4dffb67SVidya Sagar 191e4dffb67SVidya Sagarrequired: 192e4dffb67SVidya Sagar - interrupts 193e4dffb67SVidya Sagar - interrupt-names 194e4dffb67SVidya Sagar - clocks 195e4dffb67SVidya Sagar - clock-names 196e4dffb67SVidya Sagar - resets 197e4dffb67SVidya Sagar - reset-names 198e4dffb67SVidya Sagar - power-domains 199e4dffb67SVidya Sagar - reset-gpios 200e4dffb67SVidya Sagar - vddio-pex-ctl-supply 201e4dffb67SVidya Sagar - num-lanes 202e4dffb67SVidya Sagar - phys 203e4dffb67SVidya Sagar - phy-names 204e4dffb67SVidya Sagar - nvidia,bpmp 205e4dffb67SVidya Sagar 206e4dffb67SVidya Sagarexamples: 207e4dffb67SVidya Sagar - | 208e4dffb67SVidya Sagar #include <dt-bindings/clock/tegra194-clock.h> 209e4dffb67SVidya Sagar #include <dt-bindings/gpio/tegra194-gpio.h> 210e4dffb67SVidya Sagar #include <dt-bindings/interrupt-controller/arm-gic.h> 211e4dffb67SVidya Sagar #include <dt-bindings/power/tegra194-powergate.h> 212e4dffb67SVidya Sagar #include <dt-bindings/reset/tegra194-reset.h> 213e4dffb67SVidya Sagar 214e4dffb67SVidya Sagar bus@0 { 215e4dffb67SVidya Sagar #address-cells = <2>; 216e4dffb67SVidya Sagar #size-cells = <2>; 217e4dffb67SVidya Sagar ranges = <0x0 0x0 0x0 0x8 0x0>; 218e4dffb67SVidya Sagar 219e4dffb67SVidya Sagar pcie-ep@141a0000 { 220e4dffb67SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 221e4dffb67SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 222e4dffb67SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 223e4dffb67SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 224e4dffb67SVidya Sagar <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 225e4dffb67SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 226e4dffb67SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 227e4dffb67SVidya Sagar interrupt-names = "intr"; 228e4dffb67SVidya Sagar 229e4dffb67SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 230e4dffb67SVidya Sagar clock-names = "core"; 231e4dffb67SVidya Sagar 232e4dffb67SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 233e4dffb67SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 234e4dffb67SVidya Sagar reset-names = "apb", "core"; 235e4dffb67SVidya Sagar 236e4dffb67SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 237e4dffb67SVidya Sagar pinctrl-names = "default"; 238e4dffb67SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 239e4dffb67SVidya Sagar 240e4dffb67SVidya Sagar nvidia,bpmp = <&bpmp 5>; 241e4dffb67SVidya Sagar 242e4dffb67SVidya Sagar nvidia,aspm-cmrt-us = <60>; 243e4dffb67SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 244e4dffb67SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 245e4dffb67SVidya Sagar 246e4dffb67SVidya Sagar vddio-pex-ctl-supply = <&vdd_1v8ao>; 247e4dffb67SVidya Sagar 248e4dffb67SVidya Sagar reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 249e4dffb67SVidya Sagar 250e4dffb67SVidya Sagar nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 251e4dffb67SVidya Sagar GPIO_ACTIVE_HIGH>; 252e4dffb67SVidya Sagar 253e4dffb67SVidya Sagar num-lanes = <8>; 254e4dffb67SVidya Sagar 255e4dffb67SVidya Sagar phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 256e4dffb67SVidya Sagar <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 257e4dffb67SVidya Sagar <&p2u_nvhs_6>, <&p2u_nvhs_7>; 258e4dffb67SVidya Sagar 259e4dffb67SVidya Sagar phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 260e4dffb67SVidya Sagar "p2u-5", "p2u-6", "p2u-7"; 261e4dffb67SVidya Sagar }; 262e4dffb67SVidya Sagar }; 263*b949e466SVidya Sagar 264*b949e466SVidya Sagar - | 265*b949e466SVidya Sagar #include <dt-bindings/clock/tegra234-clock.h> 266*b949e466SVidya Sagar #include <dt-bindings/gpio/tegra234-gpio.h> 267*b949e466SVidya Sagar #include <dt-bindings/interrupt-controller/arm-gic.h> 268*b949e466SVidya Sagar #include <dt-bindings/power/tegra234-powergate.h> 269*b949e466SVidya Sagar #include <dt-bindings/reset/tegra234-reset.h> 270*b949e466SVidya Sagar 271*b949e466SVidya Sagar bus@0 { 272*b949e466SVidya Sagar #address-cells = <2>; 273*b949e466SVidya Sagar #size-cells = <2>; 274*b949e466SVidya Sagar ranges = <0x0 0x0 0x0 0x8 0x0>; 275*b949e466SVidya Sagar 276*b949e466SVidya Sagar pcie-ep@141a0000 { 277*b949e466SVidya Sagar compatible = "nvidia,tegra234-pcie-ep"; 278*b949e466SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 279*b949e466SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 280*b949e466SVidya Sagar <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 281*b949e466SVidya Sagar <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 282*b949e466SVidya Sagar <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 283*b949e466SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 284*b949e466SVidya Sagar 285*b949e466SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 286*b949e466SVidya Sagar interrupt-names = "intr"; 287*b949e466SVidya Sagar 288*b949e466SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 289*b949e466SVidya Sagar clock-names = "core"; 290*b949e466SVidya Sagar 291*b949e466SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 292*b949e466SVidya Sagar <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 293*b949e466SVidya Sagar reset-names = "apb", "core"; 294*b949e466SVidya Sagar 295*b949e466SVidya Sagar nvidia,bpmp = <&bpmp 5>; 296*b949e466SVidya Sagar 297*b949e466SVidya Sagar nvidia,enable-ext-refclk; 298*b949e466SVidya Sagar nvidia,aspm-cmrt-us = <60>; 299*b949e466SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 300*b949e466SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 301*b949e466SVidya Sagar 302*b949e466SVidya Sagar vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>; 303*b949e466SVidya Sagar 304*b949e466SVidya Sagar reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; 305*b949e466SVidya Sagar 306*b949e466SVidya Sagar nvidia,refclk-select-gpios = <&gpio_aon 307*b949e466SVidya Sagar TEGRA234_AON_GPIO(AA, 4) 308*b949e466SVidya Sagar GPIO_ACTIVE_HIGH>; 309*b949e466SVidya Sagar 310*b949e466SVidya Sagar num-lanes = <8>; 311*b949e466SVidya Sagar 312*b949e466SVidya Sagar phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 313*b949e466SVidya Sagar <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 314*b949e466SVidya Sagar <&p2u_nvhs_6>, <&p2u_nvhs_7>; 315*b949e466SVidya Sagar 316*b949e466SVidya Sagar phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 317*b949e466SVidya Sagar "p2u-5", "p2u-6", "p2u-7"; 318*b949e466SVidya Sagar }; 319*b949e466SVidya Sagar }; 320