1* Freescale i.MX7ULP IOMUX Controller
2
3i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
4ports and IOMUXC DDR for DDR interface.
5
6Note:
7This binding doc is only for the IOMUXC1 support in A7 Domain and it only
8supports generic pin config.
9
10Please refer to fsl,imx-pinctrl.txt in this directory for common binding
11part and usage.
12
13Required properties:
14- compatible:	"fsl,imx7ulp-iomuxc1".
15- fsl,pins:	Each entry consists of 5 integers which represents the mux
16		and config setting for one pin. The first 4 integers
17		<mux_conf_reg input_reg mux_mode input_val> are specified
18		using a PIN_FUNC_ID macro, which can be found in
19		imx7ulp-pinfunc.h in the device tree source folder.
20		The last integer CONFIG is the pad setting value like
21		pull-up on this pin.
22
23		Please refer to i.MX7ULP Reference Manual for detailed
24		CONFIG settings.
25
26CONFIG bits definition:
27PAD_CTL_OBE		(1 << 17)
28PAD_CTL_IBE		(1 << 16)
29PAD_CTL_LK		(1 << 16)
30PAD_CTL_DSE_HI		(1 << 6)
31PAD_CTL_DSE_STD		(0 << 6)
32PAD_CTL_ODE		(1 << 5)
33PAD_CTL_PUSH_PULL	(0 << 5)
34PAD_CTL_SRE_SLOW	(1 << 2)
35PAD_CTL_SRE_STD		(0 << 2)
36PAD_CTL_PE		(1 << 0)
37
38Examples:
39#include "imx7ulp-pinfunc.h"
40
41/* Pin Controller Node */
42iomuxc1: pinctrl@40ac0000 {
43	compatible = "fsl,imx7ulp-iomuxc1";
44	reg = <0x40ac0000 0x1000>;
45
46	/* Pin Configuration Node */
47	pinctrl_lpuart4: lpuart4grp {
48		fsl,pins = <
49			IMX7ULP_PAD_PTC3__LPUART4_RX	0x1
50			IMX7ULP_PAD_PTC2__LPUART4_TX	0x1
51		>;
52	};
53};
54