1Lantiq XWAY pinmux controller
2
3Required properties:
4- compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube")
5	      "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or
6					"lantiq,xrx200-pinctrl")
7	      "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl")
8	      "lantiq,<chip>-pinctrl", where <chip> is:
9		"ase" (XWAY AMAZON Family)
10		"danube" (XWAY DANUBE Family)
11		"xrx100" (XWAY xRX100 Family)
12		"xrx200" (XWAY xRX200 Family)
13		"xrx300" (XWAY xRX300 Family)
14- reg: Should contain the physical address and length of the gpio/pinmux
15  register range
16
17Please refer to pinctrl-bindings.txt in this directory for details of the
18common pinctrl bindings used by client devices, including the meaning of the
19phrase "pin configuration node".
20
21Lantiq's pin configuration nodes act as a container for an arbitrary number of
22subnodes. Each of these subnodes represents some desired configuration for a
23pin, a group, or a list of pins or groups. This configuration can include the
24mux function to select on those group(s), and two pin configuration parameters:
25pull-up and open-drain
26
27The name of each subnode is not important as long as it is unique; all subnodes
28should be enumerated and processed purely based on their content.
29
30Each subnode only affects those parameters that are explicitly listed. In
31other words, a subnode that lists a mux function but no pin configuration
32parameters implies no information about any pin configuration parameters.
33Similarly, a pin subnode that describes a pullup parameter implies no
34information about e.g. the mux function.
35
36We support 2 types of nodes.
37
38Definition of mux function groups:
39
40Required subnode-properties:
41- lantiq,groups : An array of strings. Each string contains the name of a group.
42  Valid values for these names are listed below.
43- lantiq,function: A string containing the name of the function to mux to the
44  group. Valid values for function names are listed below.
45
46Valid values for group and function names:
47
48XWAY: (DEPRECATED: Use DANUBE)
49  mux groups:
50    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
51    ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
52    spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2,
53    gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
54    req3
55
56  functions:
57    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu
58
59XR9: ( DEPRECATED: Use xRX100/xRX200)
60  mux groups:
61    exin0, exin1, exin2, exin3, exin4, jtag, ebu a23, ebu a24, ebu a25,
62    ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy,
63    nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6,
64    asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
65    clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
66    gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
67
68  functions:
69    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy
70
71AMAZON:
72  mux groups:
73    exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
74    spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
75    clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2
76
77  functions:
78    spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
79
80DANUBE:
81  mux groups:
82    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
83    ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
84    spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
85    gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
86    req1, req2, req3, dfe led0, dfe led1
87
88  functions:
89    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
90
91xRX100:
92  mux groups:
93    exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
94    ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
95    spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
96    spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
97    clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
98    dfe led0, dfe led1
99
100  functions:
101    spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
102
103xRX200:
104  mux groups:
105    exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
106    ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
107    spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
108    spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
109    usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
110    usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
111    stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
112    gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
113    gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
114
115  functions:
116    spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
117
118xRX300:
119  mux groups:
120    exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
121    nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
122    nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
123    spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
124    usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
125    mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1
126
127  functions:
128    spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
129
130
131Definition of pin configurations:
132
133Required subnode-properties:
134- lantiq,pins : An array of strings. Each string contains the name of a pin.
135  Valid values for these names are listed below.
136
137Optional subnode-properties:
138- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
139    0: none, 1: down, 2: up.
140- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
141
142Valid values for XWAY pin names: (DEPRECATED: Use DANUBE)
143  Pinconf pins can be referenced via the names io0-io31.
144
145Valid values for XR9 pin names: (DEPRECATED: Use xrX100/xRX200)
146  Pinconf pins can be referenced via the names io0-io55.
147
148Valid values for AMAZON pin names:
149  Pinconf pins can be referenced via the names io0-io31.
150
151Valid values for DANUBE pin names:
152  Pinconf pins can be referenced via the names io0-io31.
153
154Valid values for xRX100 pin names:
155  Pinconf pins can be referenced via the names io0-io55.
156
157Valid values for xRX200 pin names:
158  Pinconf pins can be referenced via the names io0-io49.
159
160Valid values for xRX300 pin names:
161  Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
162						io13-io19,io23-io27,io34-io36,
163						io42-io43,io48-io61.
164
165Example:
166	gpio: pinmux@e100b10 {
167		compatible = "lantiq,danube-pinctrl";
168		pinctrl-names = "default";
169		pinctrl-0 = <&state_default>;
170
171		#gpio-cells = <2>;
172		gpio-controller;
173		reg = <0xE100B10 0xA0>;
174
175		state_default: pinmux {
176			stp {
177				lantiq,groups = "stp";
178				lantiq,function = "stp";
179			};
180			pci {
181				lantiq,groups = "gnt1";
182				lantiq,function = "pci";
183			};
184			conf_out {
185				lantiq,pins = "io4", "io5", "io6"; /* stp */
186				lantiq,open-drain;
187				lantiq,pull = <0>;
188			};
189		};
190	};
191
192