1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SDX65 TLMM block
8
9maintainers:
10  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SDX65 SoC.
14
15properties:
16  compatible:
17    const: qcom,sdx65-tlmm
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  interrupt-controller: true
26  "#interrupt-cells": true
27  gpio-controller: true
28  "#gpio-cells": true
29  gpio-ranges: true
30
31  gpio-reserved-ranges:
32    maxItems: 1
33
34patternProperties:
35  "-state$":
36    oneOf:
37      - $ref: "#/$defs/qcom-sdx65-tlmm-state"
38      - patternProperties:
39          "-pins$":
40            $ref: "#/$defs/qcom-sdx65-tlmm-state"
41        additionalProperties: false
42
43$defs:
44  qcom-sdx65-tlmm-state:
45    type: object
46    description:
47      Pinctrl node's client devices use subnodes for desired pin configuration.
48      Client device subnodes use below standard properties.
49    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
50
51    properties:
52      pins:
53        description:
54          List of gpio pins affected by the properties specified in this subnode.
55        items:
56          oneOf:
57            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
58            - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
59        minItems: 1
60        maxItems: 150
61
62      function:
63        description:
64          Specify the alternative function to be configured for the specified
65          pins. Functions are only valid for gpio pins.
66        enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
67                bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
68                qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
69                dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
70                blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
71                mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
72                atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
73                cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
74                pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
75                qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
76                qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
77                atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
78                atest_usb20, atest_char0, dac_calib10, qdss_stm10,
79                qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
80                blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
81                qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
82                qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
83                dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
84                qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
85                dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
86                dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
87                dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
88                dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
89                sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
90                qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
91                uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
92                blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
93                qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
94                blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
95                cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
96                blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
97                qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
98                isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
99                qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
100                sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
101                gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
102                qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
103                tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
104                qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
105                sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
106                sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
107                ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
108                blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
109                pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
110                qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
111                qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
112                gpio ]
113
114      bias-pull-down: true
115      bias-pull-up: true
116      bias-disable: true
117      drive-strength: true
118      output-high: true
119      output-low: true
120
121    required:
122      - pins
123
124    additionalProperties: false
125
126allOf:
127  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
128
129required:
130  - compatible
131  - reg
132
133additionalProperties: false
134
135examples:
136  - |
137    #include <dt-bindings/interrupt-controller/arm-gic.h>
138    tlmm: pinctrl@f100000 {
139        compatible = "qcom,sdx65-tlmm";
140        reg = <0x03000000 0xdc2000>;
141        gpio-controller;
142        #gpio-cells = <2>;
143        gpio-ranges = <&tlmm 0 0 109>;
144        interrupt-controller;
145        #interrupt-cells = <2>;
146        interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
147
148        gpio-wo-subnode-state {
149            pins = "gpio1";
150            function = "gpio";
151        };
152
153        uart-w-subnodes-state {
154            rx-pins {
155                pins = "gpio4";
156                function = "blsp_uart1";
157                bias-pull-up;
158            };
159
160            tx-pins {
161                pins = "gpio5";
162                function = "blsp_uart1";
163                bias-disable;
164            };
165        };
166    };
167...
168