1===================================================================
2Debug Control and Status Register (DCSR) Binding
3Copyright 2011 Freescale Semiconductor Inc.
4
5NOTE: The bindings described in this document are preliminary and subject
6to change.  Some of the compatible strings that contain only generic names
7may turn out to be inappropriate, or need additional properties to describe
8the integration of the block with the rest of the chip.
9
10=====================================================================
11Debug Control and Status Register Memory Map
12
13Description
14
15This node defines the base address and range for the
16defined DCSR Memory Map. Child nodes will describe the individual
17debug blocks defined within this memory space.
18
19PROPERTIES
20
21	- compatible
22	Usage: required
23	Value type: <string>
24	Definition: Must include "fsl,dcsr" and "simple-bus".
25	The DCSR space exists in the memory-mapped bus.
26
27	- #address-cells
28	Usage: required
29	Value type: <u32>
30	Definition: A standard property.  Defines the number of cells
31	or representing physical addresses in child nodes.
32
33	- #size-cells
34	Usage: required
35	Value type: <u32>
36	Definition: A standard property.  Defines the number of cells
37	or representing the size of physical addresses in
38	child nodes.
39
40	- ranges
41	Usage: required
42	Value type: <prop-encoded-array>
43	Definition: A standard property. Specifies the physical address
44	range of the DCSR space.
45
46EXAMPLE
47	dcsr: dcsr@f00000000 {
48		#address-cells = <1>;
49		#size-cells = <1>;
50		compatible = "fsl,dcsr", "simple-bus";
51		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
52	};
53
54=====================================================================
55Event Processing Unit
56
57This node represents the region of DCSR space allocated to the EPU
58
59PROPERTIES
60
61	- compatible
62	Usage: required
63	Value type: <string>
64	Definition: Must include "fsl,dcsr-epu"
65
66	- interrupts
67	Usage: required
68	Value type: <prop_encoded-array>
69	Definition:  Specifies the interrupts generated by the EPU.
70	The value of the interrupts property consists of three
71	interrupt specifiers. The format of the specifier is defined
72	by the binding document describing the node's interrupt parent.
73
74	The EPU counters can be configured to assert the performance
75	monitor interrupt signal based on either counter overflow or value
76	match. Which counter asserted the interrupt is captured in an EPU
77	Counter Interrupt Status Register (EPCPUISR).
78
79	The EPU unit can also be configured to assert either or both of
80	two interrupt signals based on debug event sources within the SoC.
81	The interrupt signals are epu_xt_int0 and epu_xt_int1.
82	Which event source asserted the interrupt is captured in an EPU
83	Interrupt Status Register (EPISR0,EPISR1).
84
85	Interrupt numbers are listed in order (perfmon, event0, event1).
86
87	- reg
88	Usage: required
89	Value type: <prop-encoded-array>
90	Definition: A standard property.  Specifies the physical address
91	offset and length of the DCSR space registers of the device
92	configuration block.
93
94EXAMPLE
95	dcsr-epu@0 {
96		compatible = "fsl,dcsr-epu";
97		interrupts = <52 2 0 0
98			      84 2 0 0
99			      85 2 0 0>;
100		interrupt-parent = <&mpic>;
101		reg = <0x0 0x1000>;
102	};
103
104=======================================================================
105Nexus Port Controller
106
107This node represents the region of DCSR space allocated to the NPC
108
109PROPERTIES
110
111	- compatible
112	Usage: required
113	Value type: <string>
114	Definition: Must include "fsl,dcsr-npc"
115
116	- reg
117	Usage: required
118	Value type: <prop-encoded-array>
119	Definition: A standard property.  Specifies the physical address
120	offset and length of the DCSR space registers of the device
121	configuration block.
122	The Nexus Port controller occupies two regions in the DCSR space
123	with distinct functionality.
124
125	The first register range describes the Nexus Port Controller
126	control and status registers.
127
128	The second register range describes the Nexus Port Controller
129	internal trace buffer. The NPC trace buffer is a small memory buffer
130	which stages the nexus trace data for transmission via the Aurora port
131	or to a DDR based trace buffer. In some configurations the NPC trace
132	buffer can be the only trace buffer used.
133
134
135EXAMPLE
136		dcsr-npc {
137			compatible = "fsl,dcsr-npc";
138			reg = <0x1000 0x1000 0x1000000 0x8000>;
139		};
140
141=======================================================================
142Nexus Concentrator
143
144This node represents the region of DCSR space allocated to the NXC
145
146PROPERTIES
147
148	- compatible
149	Usage: required
150	Value type: <string>
151	Definition: Must include "fsl,dcsr-nxc"
152
153	- reg
154	Usage: required
155	Value type: <prop-encoded-array>
156	Definition: A standard property.  Specifies the physical address
157	offset and length of the DCSR space registers of the device
158	configuration block.
159
160EXAMPLE
161		dcsr-nxc@2000 {
162			compatible = "fsl,dcsr-nxc";
163			reg = <0x2000 0x1000>;
164		};
165=======================================================================
166CoreNet Debug Controller
167
168This node represents the region of DCSR space allocated to
169the CoreNet Debug controller.
170
171PROPERTIES
172
173	- compatible
174	Usage: required
175	Value type: <string>
176	Definition: Must include "fsl,dcsr-corenet"
177
178	- reg
179	Usage: required
180	Value type: <prop-encoded-array>
181	Definition: A standard property.  Specifies the physical address
182	offset and length of the DCSR space registers of the device
183	configuration block.
184	The CoreNet Debug controller occupies two regions in the DCSR space
185	with distinct functionality.
186
187	The first register range describes the CoreNet Debug Controller
188	functionalty to perform transaction and transaction attribute matches.
189
190	The second register range describes the CoreNet Debug Controller
191	functionalty to trigger event notifications and debug traces.
192
193EXAMPLE
194		dcsr-corenet {
195			compatible = "fsl,dcsr-corenet";
196			reg = <0x8000 0x1000 0xB0000 0x1000>;
197		};
198
199=======================================================================
200Data Path Debug controller
201
202This node represents the region of DCSR space allocated to
203the DPAA Debug Controller. This controller controls debug configuration
204for the QMAN and FMAN blocks.
205
206PROPERTIES
207
208	- compatible
209	Usage: required
210	Value type: <string>
211	Definition: Must include both an identifier specific to the SoC
212	or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
213	generic compatible string "fsl,dcsr-dpaa".
214
215	- reg
216	Usage: required
217	Value type: <prop-encoded-array>
218	Definition: A standard property.  Specifies the physical address
219	offset and length of the DCSR space registers of the device
220	configuration block.
221
222EXAMPLE
223		dcsr-dpaa@9000 {
224			compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
225			reg = <0x9000 0x1000>;
226		};
227
228=======================================================================
229OCeaN Debug controller
230
231This node represents the region of DCSR space allocated to
232the OCN Debug Controller.
233
234PROPERTIES
235
236	- compatible
237	Usage: required
238	Value type: <string>
239	Definition: Must include both an identifier specific to the SoC
240	or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
241	generic compatible string "fsl,dcsr-ocn".
242
243	- reg
244	Usage: required
245	Value type: <prop-encoded-array>
246	Definition: A standard property.  Specifies the physical address
247	offset and length of the DCSR space registers of the device
248	configuration block.
249
250EXAMPLE
251		dcsr-ocn@11000 {
252			compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
253			reg = <0x11000 0x1000>;
254		};
255
256=======================================================================
257DDR Controller Debug controller
258
259This node represents the region of DCSR space allocated to
260the OCN Debug Controller.
261
262PROPERTIES
263
264	- compatible
265	Usage: required
266	Value type: <string>
267	Definition: Must include "fsl,dcsr-ddr"
268
269	- dev-handle
270	Usage: required
271	Definition: A phandle to associate this debug node with its
272	component controller.
273
274	- reg
275	Usage: required
276	Value type: <prop-encoded-array>
277	Definition: A standard property.  Specifies the physical address
278	offset and length of the DCSR space registers of the device
279	configuration block.
280
281EXAMPLE
282		dcsr-ddr@12000 {
283			compatible = "fsl,dcsr-ddr";
284			dev-handle = <&ddr1>;
285			reg = <0x12000 0x1000>;
286		};
287
288=======================================================================
289Nexus Aurora Link Controller
290
291This node represents the region of DCSR space allocated to
292the NAL Controller.
293
294PROPERTIES
295
296	- compatible
297	Usage: required
298	Value type: <string>
299	Definition: Must include both an identifier specific to the SoC
300	or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
301	generic compatible string "fsl,dcsr-nal".
302
303	- reg
304	Usage: required
305	Value type: <prop-encoded-array>
306	Definition: A standard property.  Specifies the physical address
307	offset and length of the DCSR space registers of the device
308	configuration block.
309
310EXAMPLE
311		dcsr-nal@18000 {
312			compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
313			reg = <0x18000 0x1000>;
314		};
315
316
317=======================================================================
318Run Control and Power Management
319
320This node represents the region of DCSR space allocated to
321the RCPM Debug Controller. This functionlity is limited to the
322control the debug operations of the SoC and cores.
323
324PROPERTIES
325
326	- compatible
327	Usage: required
328	Value type: <string>
329	Definition: Must include both an identifier specific to the SoC
330	or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
331	generic compatible string "fsl,dcsr-rcpm".
332
333	- reg
334	Usage: required
335	Value type: <prop-encoded-array>
336	Definition: A standard property.  Specifies the physical address
337	offset and length of the DCSR space registers of the device
338	configuration block.
339
340EXAMPLE
341		dcsr-rcpm@22000 {
342			compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
343			reg = <0x22000 0x1000>;
344		};
345
346=======================================================================
347Core Service Bridge Proxy
348
349This node represents the region of DCSR space allocated to
350the Core Service Bridge Proxies.
351There is one Core Service Bridge Proxy device for each CPU in the system.
352This functionlity provides access to the debug operations of the CPU.
353
354PROPERTIES
355
356	- compatible
357	Usage: required
358	Value type: <string>
359	Definition: Must include both an identifier specific to the cpu
360	of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
361	generic compatible string "fsl,dcsr-cpu-sb-proxy".
362
363	- cpu-handle
364	Usage: required
365	Definition: A phandle to associate this debug node with its cpu.
366
367	- reg
368	Usage: required
369	Value type: <prop-encoded-array>
370	Definition: A standard property.  Specifies the physical address
371	offset and length of the DCSR space registers of the device
372	configuration block.
373
374EXAMPLE
375		dcsr-cpu-sb-proxy@40000 {
376			compatible = "fsl,dcsr-e500mc-sb-proxy",
377				     "fsl,dcsr-cpu-sb-proxy";
378			cpu-handle = <&cpu0>;
379			reg = <0x40000 0x1000>;
380		};
381		dcsr-cpu-sb-proxy@41000 {
382			compatible = "fsl,dcsr-e500mc-sb-proxy",
383				     "fsl,dcsr-cpu-sb-proxy";
384			cpu-handle = <&cpu1>;
385			reg = <0x41000 0x1000>;
386		};
387
388=======================================================================
389