1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
8
9maintainers:
10  - Conor Dooley <conor.dooley@microchip.com>
11
12description: |
13  PolarFire SoC devices include a microcontroller acting as the system controller,
14  which provides "services" to the main processor and to the FPGA fabric. These
15  services include hardware rng, reprogramming of the FPGA and verification of the
16  eNVM contents etc. More information on these services can be found online, at
17  https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
18
19  Communication with the system controller is done via a mailbox, of which the client
20  portion is documented here.
21
22properties:
23  mboxes:
24    maxItems: 1
25
26  compatible:
27    const: microchip,mpfs-sys-controller
28
29  microchip,bitstream-flash:
30    $ref: /schemas/types.yaml#/definitions/phandle
31    description:
32      The SPI flash connected to the system controller's QSPI controller.
33      The system controller may retrieve FPGA bitstreams from this flash to
34      perform In-Application Programming (IAP) or during device initialisation
35      for Auto Update. The MSS and system controller have separate QSPI
36      controllers and this flash is connected to both. Software running in the
37      MSS can write bitstreams to the flash.
38
39required:
40  - compatible
41  - mboxes
42
43additionalProperties: false
44
45examples:
46  - |
47    syscontroller {
48      compatible = "microchip,mpfs-sys-controller";
49      mboxes = <&mbox 0>;
50    };
51