1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller
8
9description:
10  The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of
11  a signal associated with an input clock into a signal associated with a
12  different output clock. The driver currently works as a Front End of DPCM
13  with other Back Ends Audio controller such as ESAI, SSI and SAI. It has
14  three pairs to support three substreams within totally 10 channels.
15
16maintainers:
17  - Shawn Guo <shawnguo@kernel.org>
18  - Sascha Hauer <s.hauer@pengutronix.de>
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - fsl,imx35-asrc
25          - fsl,imx53-asrc
26          - fsl,imx8qm-asrc
27          - fsl,imx8qxp-asrc
28      - items:
29          - enum:
30              - fsl,imx6sx-asrc
31              - fsl,imx6ul-asrc
32          - const: fsl,imx53-asrc
33
34  reg:
35    maxItems: 1
36
37  interrupts:
38    maxItems: 1
39
40  dmas:
41    maxItems: 6
42
43  dma-names:
44    items:
45      - const: rxa
46      - const: rxb
47      - const: rxc
48      - const: txa
49      - const: txb
50      - const: txc
51
52  clocks:
53    maxItems: 19
54
55  clock-names:
56    items:
57      - const: mem
58      - const: ipg
59      - const: asrck_0
60      - const: asrck_1
61      - const: asrck_2
62      - const: asrck_3
63      - const: asrck_4
64      - const: asrck_5
65      - const: asrck_6
66      - const: asrck_7
67      - const: asrck_8
68      - const: asrck_9
69      - const: asrck_a
70      - const: asrck_b
71      - const: asrck_c
72      - const: asrck_d
73      - const: asrck_e
74      - const: asrck_f
75      - const: spba
76
77  fsl,asrc-rate:
78    $ref: /schemas/types.yaml#/definitions/uint32
79    description: The mutual sample rate used by DPCM Back Ends
80
81  fsl,asrc-width:
82    $ref: /schemas/types.yaml#/definitions/uint32
83    description: The mutual sample width used by DPCM Back Ends
84    enum: [16, 24]
85
86  fsl,asrc-clk-map:
87    $ref: /schemas/types.yaml#/definitions/uint32
88    description:
89      Defines clock map used in driver
90      <0> - select the map for asrc0 in imx8qm/imx8qxp
91      <1> - select the map for asrc1 in imx8qm/imx8qxp
92    enum: [0, 1]
93
94  big-endian:
95    type: boolean
96    description:
97      If this property is absent, the little endian mode will be in use as
98      default. Otherwise, the big endian mode will be in use for all the
99      device registers.
100
101  fsl,asrc-format:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      Defines a mutual sample format used by DPCM Back Ends, which can
105      replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE).
106    enum: [2, 6]
107
108required:
109  - compatible
110  - reg
111  - interrupts
112  - dmas
113  - dma-names
114  - clocks
115  - clock-names
116  - fsl,asrc-rate
117  - fsl,asrc-width
118
119allOf:
120  - if:
121      properties:
122        compatible:
123          contains:
124            enum:
125              - fsl,imx8qm-asrc
126              - fsl,imx8qxp-asrc
127    then:
128      required:
129        - fsl,asrc-clk-map
130    else:
131      properties:
132        fsl,asrc-clk-map: false
133
134additionalProperties: false
135
136examples:
137  - |
138    #include <dt-bindings/interrupt-controller/irq.h>
139    #include <dt-bindings/clock/imx6qdl-clock.h>
140    asrc: asrc@2034000 {
141        compatible = "fsl,imx53-asrc";
142        reg = <0x02034000 0x4000>;
143        interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
144        clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
145                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
146                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
147                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
148                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
149                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
150                 <&clks IMX6QDL_CLK_SPBA>;
151        clock-names = "mem", "ipg", "asrck_0",
152                "asrck_1", "asrck_2", "asrck_3", "asrck_4",
153                "asrck_5", "asrck_6", "asrck_7", "asrck_8",
154                "asrck_9", "asrck_a", "asrck_b", "asrck_c",
155                "asrck_d", "asrck_e", "asrck_f", "spba";
156        dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
157               <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
158        dma-names = "rxa", "rxb", "rxc",
159                    "txa", "txb", "txc";
160        fsl,asrc-rate  = <48000>;
161        fsl,asrc-width = <16>;
162    };
163