1===================== 2PHY Abstraction Layer 3===================== 4 5Purpose 6======= 7 8Most network devices consist of set of registers which provide an interface 9to a MAC layer, which communicates with the physical connection through a 10PHY. The PHY concerns itself with negotiating link parameters with the link 11partner on the other side of the network connection (typically, an ethernet 12cable), and provides a register interface to allow drivers to determine what 13settings were chosen, and to configure what settings are allowed. 14 15While these devices are distinct from the network devices, and conform to a 16standard layout for the registers, it has been common practice to integrate 17the PHY management code with the network driver. This has resulted in large 18amounts of redundant code. Also, on embedded systems with multiple (and 19sometimes quite different) ethernet controllers connected to the same 20management bus, it is difficult to ensure safe use of the bus. 21 22Since the PHYs are devices, and the management busses through which they are 23accessed are, in fact, busses, the PHY Abstraction Layer treats them as such. 24In doing so, it has these goals: 25 26#. Increase code-reuse 27#. Increase overall code-maintainability 28#. Speed development time for new network drivers, and for new systems 29 30Basically, this layer is meant to provide an interface to PHY devices which 31allows network driver writers to write as little code as possible, while 32still providing a full feature set. 33 34The MDIO bus 35============ 36 37Most network devices are connected to a PHY by means of a management bus. 38Different devices use different busses (though some share common interfaces). 39In order to take advantage of the PAL, each bus interface needs to be 40registered as a distinct device. 41 42#. read and write functions must be implemented. Their prototypes are:: 43 44 int write(struct mii_bus *bus, int mii_id, int regnum, u16 value); 45 int read(struct mii_bus *bus, int mii_id, int regnum); 46 47 mii_id is the address on the bus for the PHY, and regnum is the register 48 number. These functions are guaranteed not to be called from interrupt 49 time, so it is safe for them to block, waiting for an interrupt to signal 50 the operation is complete 51 52#. A reset function is optional. This is used to return the bus to an 53 initialized state. 54 55#. A probe function is needed. This function should set up anything the bus 56 driver needs, setup the mii_bus structure, and register with the PAL using 57 mdiobus_register. Similarly, there's a remove function to undo all of 58 that (use mdiobus_unregister). 59 60#. Like any driver, the device_driver structure must be configured, and init 61 exit functions are used to register the driver. 62 63#. The bus must also be declared somewhere as a device, and registered. 64 65As an example for how one driver implemented an mdio bus driver, see 66drivers/net/ethernet/freescale/fsl_pq_mdio.c and an associated DTS file 67for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/") 68 69(RG)MII/electrical interface considerations 70=========================================== 71 72The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin 73electrical signal interface using a synchronous 125Mhz clock signal and several 74data lines. Due to this design decision, a 1.5ns to 2ns delay must be added 75between the clock line (RXC or TXC) and the data lines to let the PHY (clock 76sink) have enough setup and hold times to sample the data lines correctly. The 77PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let 78the PHY driver and optionally the MAC driver, implement the required delay. The 79values of phy_interface_t must be understood from the perspective of the PHY 80device itself, leading to the following: 81 82* PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting any 83 internal delay by itself, it assumes that either the Ethernet MAC (if capable 84 or the PCB traces) insert the correct 1.5-2ns delay 85 86* PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay 87 for the transmit data lines (TXD[3:0]) processed by the PHY device 88 89* PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delay 90 for the receive data lines (RXD[3:0]) processed by the PHY device 91 92* PHY_INTERFACE_MODE_RGMII_ID: the PHY should insert internal delays for 93 both transmit AND receive data lines from/to the PHY device 94 95Whenever possible, use the PHY side RGMII delay for these reasons: 96 97* PHY devices may offer sub-nanosecond granularity in how they allow a 98 receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such 99 precision may be required to account for differences in PCB trace lengths 100 101* PHY devices are typically qualified for a large range of applications 102 (industrial, medical, automotive...), and they provide a constant and 103 reliable delay across temperature/pressure/voltage ranges 104 105* PHY device drivers in PHYLIB being reusable by nature, being able to 106 configure correctly a specified delay enables more designs with similar delay 107 requirements to be operate correctly 108 109For cases where the PHY is not capable of providing this delay, but the 110Ethernet MAC driver is capable of doing so, the correct phy_interface_t value 111should be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should be 112configured correctly in order to provide the required transmit and/or receive 113side delay from the perspective of the PHY device. Conversely, if the Ethernet 114MAC driver looks at the phy_interface_t value, for any other mode but 115PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are 116disabled. 117 118In case neither the Ethernet MAC, nor the PHY are capable of providing the 119required delays, as defined per the RGMII standard, several options may be 120available: 121 122* Some SoCs may offer a pin pad/mux/controller capable of configuring a given 123 set of pins'strength, delays, and voltage; and it may be a suitable 124 option to insert the expected 2ns RGMII delay. 125 126* Modifying the PCB design to include a fixed delay (e.g: using a specifically 127 designed serpentine), which may not require software configuration at all. 128 129Common problems with RGMII delay mismatch 130----------------------------------------- 131 132When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this 133will most likely result in the clock and data line signals to be unstable when 134the PHY or MAC take a snapshot of these signals to translate them into logical 1351 or 0 states and reconstruct the data being transmitted/received. Typical 136symptoms include: 137 138* Transmission/reception partially works, and there is frequent or occasional 139 packet loss observed 140 141* Ethernet MAC may report some or all packets ingressing with a FCS/CRC error, 142 or just discard them all 143 144* Switching to lower speeds such as 10/100Mbits/sec makes the problem go away 145 (since there is enough setup/hold time in that case) 146 147Connecting to a PHY 148=================== 149 150Sometime during startup, the network driver needs to establish a connection 151between the PHY device, and the network device. At this time, the PHY's bus 152and drivers need to all have been loaded, so it is ready for the connection. 153At this point, there are several ways to connect to the PHY: 154 155#. The PAL handles everything, and only calls the network driver when 156 the link state changes, so it can react. 157 158#. The PAL handles everything except interrupts (usually because the 159 controller has the interrupt registers). 160 161#. The PAL handles everything, but checks in with the driver every second, 162 allowing the network driver to react first to any changes before the PAL 163 does. 164 165#. The PAL serves only as a library of functions, with the network device 166 manually calling functions to update status, and configure the PHY 167 168 169Letting the PHY Abstraction Layer do Everything 170=============================================== 171 172If you choose option 1 (The hope is that every driver can, but to still be 173useful to drivers that can't), connecting to the PHY is simple: 174 175First, you need a function to react to changes in the link state. This 176function follows this protocol:: 177 178 static void adjust_link(struct net_device *dev); 179 180Next, you need to know the device name of the PHY connected to this device. 181The name will look something like, "0:00", where the first number is the 182bus id, and the second is the PHY's address on that bus. Typically, 183the bus is responsible for making its ID unique. 184 185Now, to connect, just call this function:: 186 187 phydev = phy_connect(dev, phy_name, &adjust_link, interface); 188 189*phydev* is a pointer to the phy_device structure which represents the PHY. 190If phy_connect is successful, it will return the pointer. dev, here, is the 191pointer to your net_device. Once done, this function will have started the 192PHY's software state machine, and registered for the PHY's interrupt, if it 193has one. The phydev structure will be populated with information about the 194current state, though the PHY will not yet be truly operational at this 195point. 196 197PHY-specific flags should be set in phydev->dev_flags prior to the call 198to phy_connect() such that the underlying PHY driver can check for flags 199and perform specific operations based on them. 200This is useful if the system has put hardware restrictions on 201the PHY/controller, of which the PHY needs to be aware. 202 203*interface* is a u32 which specifies the connection type used 204between the controller and the PHY. Examples are GMII, MII, 205RGMII, and SGMII. For a full list, see include/linux/phy.h 206 207Now just make sure that phydev->supported and phydev->advertising have any 208values pruned from them which don't make sense for your controller (a 10/100 209controller may be connected to a gigabit capable PHY, so you would need to 210mask off SUPPORTED_1000baseT*). See include/linux/ethtool.h for definitions 211for these bitfields. Note that you should not SET any bits, except the 212SUPPORTED_Pause and SUPPORTED_AsymPause bits (see below), or the PHY may get 213put into an unsupported state. 214 215Lastly, once the controller is ready to handle network traffic, you call 216phy_start(phydev). This tells the PAL that you are ready, and configures the 217PHY to connect to the network. If the MAC interrupt of your network driver 218also handles PHY status changes, just set phydev->irq to PHY_IGNORE_INTERRUPT 219before you call phy_start and use phy_mac_interrupt() from the network 220driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL. 221phy_start() enables the PHY interrupts (if applicable) and starts the 222phylib state machine. 223 224When you want to disconnect from the network (even if just briefly), you call 225phy_stop(phydev). This function also stops the phylib state machine and 226disables PHY interrupts. 227 228Pause frames / flow control 229=========================== 230 231The PHY does not participate directly in flow control/pause frames except by 232making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in 233MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC 234controller supports such a thing. Since flow control/pause frames generation 235involves the Ethernet MAC driver, it is recommended that this driver takes care 236of properly indicating advertisement and support for such features by setting 237the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done 238either before or after phy_connect() and/or as a result of implementing the 239ethtool::set_pauseparam feature. 240 241 242Keeping Close Tabs on the PAL 243============================= 244 245It is possible that the PAL's built-in state machine needs a little help to 246keep your network device and the PHY properly in sync. If so, you can 247register a helper function when connecting to the PHY, which will be called 248every second before the state machine reacts to any changes. To do this, you 249need to manually call phy_attach() and phy_prepare_link(), and then call 250phy_start_machine() with the second argument set to point to your special 251handler. 252 253Currently there are no examples of how to use this functionality, and testing 254on it has been limited because the author does not have any drivers which use 255it (they all use option 1). So Caveat Emptor. 256 257Doing it all yourself 258===================== 259 260There's a remote chance that the PAL's built-in state machine cannot track 261the complex interactions between the PHY and your network device. If this is 262so, you can simply call phy_attach(), and not call phy_start_machine or 263phy_prepare_link(). This will mean that phydev->state is entirely yours to 264handle (phy_start and phy_stop toggle between some of the states, so you 265might need to avoid them). 266 267An effort has been made to make sure that useful functionality can be 268accessed without the state-machine running, and most of these functions are 269descended from functions which did not interact with a complex state-machine. 270However, again, no effort has been made so far to test running without the 271state machine, so tryer beware. 272 273Here is a brief rundown of the functions:: 274 275 int phy_read(struct phy_device *phydev, u16 regnum); 276 int phy_write(struct phy_device *phydev, u16 regnum, u16 val); 277 278Simple read/write primitives. They invoke the bus's read/write function 279pointers. 280:: 281 282 void phy_print_status(struct phy_device *phydev); 283 284A convenience function to print out the PHY status neatly. 285:: 286 287 void phy_request_interrupt(struct phy_device *phydev); 288 289Requests the IRQ for the PHY interrupts. 290:: 291 292 struct phy_device * phy_attach(struct net_device *dev, const char *phy_id, 293 phy_interface_t interface); 294 295Attaches a network device to a particular PHY, binding the PHY to a generic 296driver if none was found during bus initialization. 297:: 298 299 int phy_start_aneg(struct phy_device *phydev); 300 301Using variables inside the phydev structure, either configures advertising 302and resets autonegotiation, or disables autonegotiation, and configures 303forced settings. 304:: 305 306 static inline int phy_read_status(struct phy_device *phydev); 307 308Fills the phydev structure with up-to-date information about the current 309settings in the PHY. 310:: 311 312 int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); 313 314Ethtool convenience functions. 315:: 316 317 int phy_mii_ioctl(struct phy_device *phydev, 318 struct mii_ioctl_data *mii_data, int cmd); 319 320The MII ioctl. Note that this function will completely screw up the state 321machine if you write registers like BMCR, BMSR, ADVERTISE, etc. Best to 322use this only to write registers which are not standard, and don't set off 323a renegotiation. 324 325PHY Device Drivers 326================== 327 328With the PHY Abstraction Layer, adding support for new PHYs is 329quite easy. In some cases, no work is required at all! However, 330many PHYs require a little hand-holding to get up-and-running. 331 332Generic PHY driver 333------------------ 334 335If the desired PHY doesn't have any errata, quirks, or special 336features you want to support, then it may be best to not add 337support, and let the PHY Abstraction Layer's Generic PHY Driver 338do all of the work. 339 340Writing a PHY driver 341-------------------- 342 343If you do need to write a PHY driver, the first thing to do is 344make sure it can be matched with an appropriate PHY device. 345This is done during bus initialization by reading the device's 346UID (stored in registers 2 and 3), then comparing it to each 347driver's phy_id field by ANDing it with each driver's 348phy_id_mask field. Also, it needs a name. Here's an example:: 349 350 static struct phy_driver dm9161_driver = { 351 .phy_id = 0x0181b880, 352 .name = "Davicom DM9161E", 353 .phy_id_mask = 0x0ffffff0, 354 ... 355 } 356 357Next, you need to specify what features (speed, duplex, autoneg, 358etc) your PHY device and driver support. Most PHYs support 359PHY_BASIC_FEATURES, but you can look in include/mii.h for other 360features. 361 362Each driver consists of a number of function pointers, documented 363in include/linux/phy.h under the phy_driver structure. 364 365Of these, only config_aneg and read_status are required to be 366assigned by the driver code. The rest are optional. Also, it is 367preferred to use the generic phy driver's versions of these two 368functions if at all possible: genphy_read_status and 369genphy_config_aneg. If this is not possible, it is likely that 370you only need to perform some actions before and after invoking 371these functions, and so your functions will wrap the generic 372ones. 373 374Feel free to look at the Marvell, Cicada, and Davicom drivers in 375drivers/net/phy/ for examples (the lxt and qsemi drivers have 376not been tested as of this writing). 377 378The PHY's MMD register accesses are handled by the PAL framework 379by default, but can be overridden by a specific PHY driver if 380required. This could be the case if a PHY was released for 381manufacturing before the MMD PHY register definitions were 382standardized by the IEEE. Most modern PHYs will be able to use 383the generic PAL framework for accessing the PHY's MMD registers. 384An example of such usage is for Energy Efficient Ethernet support, 385implemented in the PAL. This support uses the PAL to access MMD 386registers for EEE query and configuration if the PHY supports 387the IEEE standard access mechanisms, or can use the PHY's specific 388access interfaces if overridden by the specific PHY driver. See 389the Micrel driver in drivers/net/phy/ for an example of how this 390can be implemented. 391 392Board Fixups 393============ 394 395Sometimes the specific interaction between the platform and the PHY requires 396special handling. For instance, to change where the PHY's clock input is, 397or to add a delay to account for latency issues in the data path. In order 398to support such contingencies, the PHY Layer allows platform code to register 399fixups to be run when the PHY is brought up (or subsequently reset). 400 401When the PHY Layer brings up a PHY it checks to see if there are any fixups 402registered for it, matching based on UID (contained in the PHY device's phy_id 403field) and the bus identifier (contained in phydev->dev.bus_id). Both must 404match, however two constants, PHY_ANY_ID and PHY_ANY_UID, are provided as 405wildcards for the bus ID and UID, respectively. 406 407When a match is found, the PHY layer will invoke the run function associated 408with the fixup. This function is passed a pointer to the phy_device of 409interest. It should therefore only operate on that PHY. 410 411The platform code can either register the fixup using phy_register_fixup():: 412 413 int phy_register_fixup(const char *phy_id, 414 u32 phy_uid, u32 phy_uid_mask, 415 int (*run)(struct phy_device *)); 416 417Or using one of the two stubs, phy_register_fixup_for_uid() and 418phy_register_fixup_for_id():: 419 420 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask, 421 int (*run)(struct phy_device *)); 422 int phy_register_fixup_for_id(const char *phy_id, 423 int (*run)(struct phy_device *)); 424 425The stubs set one of the two matching criteria, and set the other one to 426match anything. 427 428When phy_register_fixup() or \*_for_uid()/\*_for_id() is called at module, 429unregister fixup and free allocate memory are required. 430 431Call one of following function before unloading module:: 432 433 int phy_unregister_fixup(const char *phy_id, u32 phy_uid, u32 phy_uid_mask); 434 int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask); 435 int phy_register_fixup_for_id(const char *phy_id); 436 437Standards 438========= 439 440IEEE Standard 802.3: CSMA/CD Access Method and Physical Layer Specifications, Section Two: 441http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf 442 443RGMII v1.3: 444http://web.archive.org/web/20160303212629/http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf 445 446RGMII v2.0: 447http://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf 448