1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2820970a5SVineet Gupta /*
3820970a5SVineet Gupta * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com)
4820970a5SVineet Gupta */
5820970a5SVineet Gupta
6820970a5SVineet Gupta #include <linux/interrupt.h>
7820970a5SVineet Gupta #include <linux/module.h>
8820970a5SVineet Gupta #include <linux/of.h>
9820970a5SVineet Gupta #include <linux/irqdomain.h>
10820970a5SVineet Gupta #include <linux/irqchip.h>
11820970a5SVineet Gupta #include <asm/irq.h>
12820970a5SVineet Gupta
13179cf194SVineet Gupta #define NR_EXCEPTIONS 16
14179cf194SVineet Gupta
15179cf194SVineet Gupta struct bcr_irq_arcv2 {
16179cf194SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
17179cf194SVineet Gupta unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
18179cf194SVineet Gupta #else
19179cf194SVineet Gupta unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
20179cf194SVineet Gupta #endif
21179cf194SVineet Gupta };
22fe7b1099SVineet Gupta
23820970a5SVineet Gupta /*
24820970a5SVineet Gupta * Early Hardware specific Interrupt setup
25820970a5SVineet Gupta * -Called very early (start_kernel -> setup_arch -> setup_processor)
26820970a5SVineet Gupta * -Platform Independent (must for any ARC Core)
27820970a5SVineet Gupta * -Needed for each CPU (hence not foldable into init_IRQ)
28820970a5SVineet Gupta */
arc_init_IRQ(void)29820970a5SVineet Gupta void arc_init_IRQ(void)
30820970a5SVineet Gupta {
31be568e78SYuriy Kolerov unsigned int tmp, irq_prio, i;
32179cf194SVineet Gupta struct bcr_irq_arcv2 irq_bcr;
33dec2b284SVineet Gupta
34820970a5SVineet Gupta struct aux_irq_ctrl {
35820970a5SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
36820970a5SVineet Gupta unsigned int res3:18, save_idx_regs:1, res2:1,
37820970a5SVineet Gupta save_u_to_u:1, save_lp_regs:1, save_blink:1,
38820970a5SVineet Gupta res:4, save_nr_gpr_pairs:5;
39820970a5SVineet Gupta #else
40820970a5SVineet Gupta unsigned int save_nr_gpr_pairs:5, res:4,
41820970a5SVineet Gupta save_blink:1, save_lp_regs:1, save_u_to_u:1,
42820970a5SVineet Gupta res2:1, save_idx_regs:1, res3:18;
43820970a5SVineet Gupta #endif
44820970a5SVineet Gupta } ictrl;
45820970a5SVineet Gupta
46820970a5SVineet Gupta *(unsigned int *)&ictrl = 0;
47820970a5SVineet Gupta
48e494239aSVineet Gupta #ifndef CONFIG_ARC_IRQ_NO_AUTOSAVE
49820970a5SVineet Gupta ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */
50820970a5SVineet Gupta ictrl.save_blink = 1;
51820970a5SVineet Gupta ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */
52820970a5SVineet Gupta ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */
53820970a5SVineet Gupta ictrl.save_idx_regs = 1; /* JLI, LDI, EI */
54e494239aSVineet Gupta #endif
55820970a5SVineet Gupta
56820970a5SVineet Gupta WRITE_AUX(AUX_IRQ_CTRL, ictrl);
57820970a5SVineet Gupta
58820970a5SVineet Gupta /*
59820970a5SVineet Gupta * ARCv2 core intc provides multiple interrupt priorities (up to 16).
60820970a5SVineet Gupta * Typical builds though have only two levels (0-high, 1-low)
61820970a5SVineet Gupta * Linux by default uses lower prio 1 for most irqs, reserving 0 for
62820970a5SVineet Gupta * NMI style interrupts in future (say perf)
63820970a5SVineet Gupta */
64dec2b284SVineet Gupta
65dec2b284SVineet Gupta READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
66dec2b284SVineet Gupta
67dec2b284SVineet Gupta irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
68dec2b284SVineet Gupta pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
69107177b1SVineet Gupta irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
70dec2b284SVineet Gupta irq_bcr.firq ? " FIRQ (not used)":"");
71dec2b284SVineet Gupta
72be568e78SYuriy Kolerov /*
73be568e78SYuriy Kolerov * Set a default priority for all available interrupts to prevent
74be568e78SYuriy Kolerov * switching of register banks if Fast IRQ and multiple register banks
75be568e78SYuriy Kolerov * are supported by CPU.
76e8206d2bSAlexey Brodkin * Also disable private-per-core IRQ lines so faulty external HW won't
77a8ec3ee8SAlexey Brodkin * trigger interrupt that kernel is not ready to handle.
78be568e78SYuriy Kolerov */
79be568e78SYuriy Kolerov for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
80be568e78SYuriy Kolerov write_aux_reg(AUX_IRQ_SELECT, i);
81be568e78SYuriy Kolerov write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
82e8206d2bSAlexey Brodkin
83e8206d2bSAlexey Brodkin /*
84e8206d2bSAlexey Brodkin * Only mask cpu private IRQs here.
85e8206d2bSAlexey Brodkin * "common" interrupts are masked at IDU, otherwise it would
86e8206d2bSAlexey Brodkin * need to be unmasked at each cpu, with IPIs
87e8206d2bSAlexey Brodkin */
88e8206d2bSAlexey Brodkin if (i < FIRST_EXT_IRQ)
89a8ec3ee8SAlexey Brodkin write_aux_reg(AUX_IRQ_ENABLE, 0);
90be568e78SYuriy Kolerov }
91be568e78SYuriy Kolerov
92dec2b284SVineet Gupta /* setup status32, don't enable intr yet as kernel doesn't want */
93e98a7bf0SYuriy Kolerov tmp = read_aux_reg(ARC_REG_STATUS32);
9476551468SEugeniy Paltsev tmp |= ARCV2_IRQ_DEF_PRIO << 1;
95dec2b284SVineet Gupta tmp &= ~STATUS_IE_MASK;
96bc0c7eceSYuriy Kolerov asm volatile("kflag %0 \n"::"r"(tmp));
97820970a5SVineet Gupta }
98820970a5SVineet Gupta
arcv2_irq_mask(struct irq_data * data)99820970a5SVineet Gupta static void arcv2_irq_mask(struct irq_data *data)
100820970a5SVineet Gupta {
1012163266cSYuriy Kolerov write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
102820970a5SVineet Gupta write_aux_reg(AUX_IRQ_ENABLE, 0);
103820970a5SVineet Gupta }
104820970a5SVineet Gupta
arcv2_irq_unmask(struct irq_data * data)105820970a5SVineet Gupta static void arcv2_irq_unmask(struct irq_data *data)
106820970a5SVineet Gupta {
1072163266cSYuriy Kolerov write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
108820970a5SVineet Gupta write_aux_reg(AUX_IRQ_ENABLE, 1);
109820970a5SVineet Gupta }
110820970a5SVineet Gupta
arcv2_irq_enable(struct irq_data * data)111*4d369680SVineet Gupta static void arcv2_irq_enable(struct irq_data *data)
112820970a5SVineet Gupta {
113820970a5SVineet Gupta /* set default priority */
1142163266cSYuriy Kolerov write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
115107177b1SVineet Gupta write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
116820970a5SVineet Gupta
117820970a5SVineet Gupta /*
118820970a5SVineet Gupta * hw auto enables (linux unmask) all by default
119820970a5SVineet Gupta * So no need to do IRQ_ENABLE here
120820970a5SVineet Gupta * XXX: However OSCI LAN need it
121820970a5SVineet Gupta */
122820970a5SVineet Gupta write_aux_reg(AUX_IRQ_ENABLE, 1);
123820970a5SVineet Gupta }
124820970a5SVineet Gupta
125820970a5SVineet Gupta static struct irq_chip arcv2_irq_chip = {
126820970a5SVineet Gupta .name = "ARCv2 core Intc",
127820970a5SVineet Gupta .irq_mask = arcv2_irq_mask,
128820970a5SVineet Gupta .irq_unmask = arcv2_irq_unmask,
129820970a5SVineet Gupta .irq_enable = arcv2_irq_enable
130820970a5SVineet Gupta };
131820970a5SVineet Gupta
arcv2_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)132820970a5SVineet Gupta static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
133820970a5SVineet Gupta irq_hw_number_t hw)
134820970a5SVineet Gupta {
1358eb0984bSVineet Gupta /*
1368eb0984bSVineet Gupta * core intc IRQs [16, 23]:
1378eb0984bSVineet Gupta * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
1388eb0984bSVineet Gupta */
139179cf194SVineet Gupta if (hw < FIRST_EXT_IRQ) {
1408eb0984bSVineet Gupta /*
1418eb0984bSVineet Gupta * A subsequent request_percpu_irq() fails if percpu_devid is
1428eb0984bSVineet Gupta * not set. That in turns sets NOAUTOEN, meaning each core needs
1438eb0984bSVineet Gupta * to call enable_percpu_irq()
1448eb0984bSVineet Gupta */
1458eb0984bSVineet Gupta irq_set_percpu_devid(irq);
146820970a5SVineet Gupta irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);
1478eb0984bSVineet Gupta } else {
148820970a5SVineet Gupta irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);
1498eb0984bSVineet Gupta }
150820970a5SVineet Gupta
151820970a5SVineet Gupta return 0;
152820970a5SVineet Gupta }
153820970a5SVineet Gupta
154820970a5SVineet Gupta static const struct irq_domain_ops arcv2_irq_ops = {
155820970a5SVineet Gupta .xlate = irq_domain_xlate_onecell,
156820970a5SVineet Gupta .map = arcv2_irq_map,
157820970a5SVineet Gupta };
158820970a5SVineet Gupta
159820970a5SVineet Gupta
160820970a5SVineet Gupta static int __init
init_onchip_IRQ(struct device_node * intc,struct device_node * parent)161820970a5SVineet Gupta init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
162820970a5SVineet Gupta {
1631b0ccb8aSVineet Gupta struct irq_domain *root_domain;
164179cf194SVineet Gupta struct bcr_irq_arcv2 irq_bcr;
165179cf194SVineet Gupta unsigned int nr_cpu_irqs;
166179cf194SVineet Gupta
167179cf194SVineet Gupta READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
168179cf194SVineet Gupta nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
1691b0ccb8aSVineet Gupta
170820970a5SVineet Gupta if (parent)
171820970a5SVineet Gupta panic("DeviceTree incore intc not a root irq controller\n");
172820970a5SVineet Gupta
173179cf194SVineet Gupta root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
174820970a5SVineet Gupta if (!root_domain)
175820970a5SVineet Gupta panic("root irq domain not avail\n");
176820970a5SVineet Gupta
1771b0ccb8aSVineet Gupta /*
1781b0ccb8aSVineet Gupta * Needed for primary domain lookup to succeed
1791b0ccb8aSVineet Gupta * This is a primary irqchip, and can never have a parent
1801b0ccb8aSVineet Gupta */
181820970a5SVineet Gupta irq_set_default_host(root_domain);
182820970a5SVineet Gupta
183d21beffbSVineet Gupta #ifdef CONFIG_SMP
184d21beffbSVineet Gupta irq_create_mapping(root_domain, IPI_IRQ);
185d21beffbSVineet Gupta #endif
186d21beffbSVineet Gupta irq_create_mapping(root_domain, SOFTIRQ_IRQ);
187d21beffbSVineet Gupta
188820970a5SVineet Gupta return 0;
189820970a5SVineet Gupta }
190820970a5SVineet Gupta
191820970a5SVineet Gupta IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);
192