1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10 11/ { 12 model = "Toradex Colibri iMX6DL/S Module"; 13 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; 14 15 aliases { 16 mmc0 = &usdhc3; /* eMMC */ 17 mmc1 = &usdhc1; /* MMC/SD Slot */ 18 /delete-property/ mmc2; 19 /delete-property/ mmc3; 20 }; 21 22 backlight: backlight { 23 compatible = "pwm-backlight"; 24 brightness-levels = <0 45 63 88 119 158 203 255>; 25 default-brightness-level = <4>; 26 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_gpio_bl_on>; 29 power-supply = <®_module_3v3>; 30 pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 extcon_usbc_det: usbc-det { 35 compatible = "linux,extcon-usb-gpio"; 36 id-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_usbc_det>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ 49 label = "Wake-Up"; 50 linux,code = <KEY_WAKEUP>; 51 wakeup-source; 52 }; 53 }; 54 55 lcd_display: disp0 { 56 compatible = "fsl,imx-parallel-display"; 57 interface-pix-fmt = "bgr666"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 60 status = "disabled"; 61 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 port@0 { 66 reg = <0>; 67 68 lcd_display_in: endpoint { 69 remote-endpoint = <&ipu1_di0_disp0>; 70 }; 71 }; 72 73 port@1 { 74 reg = <1>; 75 76 lcd_display_out: endpoint { 77 remote-endpoint = <&lcd_panel_in>; 78 }; 79 }; 80 }; 81 82 /* Will be filled by the bootloader */ 83 memory@10000000 { 84 device_type = "memory"; 85 reg = <0x10000000 0>; 86 }; 87 88 panel_dpi: panel-dpi { 89 /* 90 * edt,et057090dhu: EDT 5.7" LCD TFT 91 * edt,et070080dh6: EDT 7.0" LCD TFT 92 */ 93 compatible = "edt,et057090dhu"; 94 backlight = <&backlight>; 95 status = "disabled"; 96 97 port { 98 lcd_panel_in: endpoint { 99 remote-endpoint = <&lcd_display_out>; 100 }; 101 }; 102 }; 103 104 reg_module_3v3: regulator-module-3v3 { 105 compatible = "regulator-fixed"; 106 regulator-name = "+V3.3"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 regulator-always-on; 110 }; 111 112 reg_module_3v3_audio: regulator-module-3v3-audio { 113 compatible = "regulator-fixed"; 114 regulator-name = "+V3.3_AUDIO"; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 regulator-always-on; 118 }; 119 120 reg_usb_host_vbus: regulator-usb-host-vbus { 121 compatible = "regulator-fixed"; 122 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 125 regulator-max-microvolt = <5000000>; 126 regulator-min-microvolt = <5000000>; 127 regulator-name = "usb_host_vbus"; 128 status = "disabled"; 129 }; 130 131 sound { 132 compatible = "fsl,imx-audio-sgtl5000"; 133 audio-codec = <&codec>; 134 audio-routing = 135 "Headphone Jack", "HP_OUT", 136 "LINE_IN", "Line In Jack", 137 "MIC_IN", "Mic Jack", 138 "Mic Jack", "Mic Bias"; 139 model = "imx6dl-colibri-sgtl5000"; 140 mux-int-port = <1>; 141 mux-ext-port = <5>; 142 ssi-controller = <&ssi1>; 143 }; 144 145 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ 146 sound_spdif: sound-spdif { 147 compatible = "fsl,imx-audio-spdif"; 148 spdif-controller = <&spdif>; 149 spdif-in; 150 spdif-out; 151 model = "imx-spdif"; 152 status = "disabled"; 153 }; 154}; 155 156&audmux { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; 159 status = "okay"; 160}; 161 162/* Optional on SODIMM 55/63 */ 163&can1 { 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_flexcan1>; 166 status = "disabled"; 167}; 168 169/* Optional on SODIMM 178/188 */ 170&can2 { 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_flexcan2>; 173 status = "disabled"; 174}; 175 176&clks { 177 fsl,pmic-stby-poweroff; 178}; 179 180/* Colibri SSP */ 181&ecspi4 { 182 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_ecspi4>; 185 status = "disabled"; 186}; 187 188&fec { 189 phy-mode = "rmii"; 190 phy-handle = <ðphy>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_enet>; 193 status = "okay"; 194 195 mdio { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 ethphy: ethernet-phy@0 { 200 reg = <0>; 201 micrel,led-mode = <0>; 202 }; 203 }; 204}; 205 206&gpio1 { 207 gpio-line-names = "", 208 "SODIMM_67", 209 "SODIMM_180", 210 "SODIMM_196", 211 "SODIMM_174", 212 "SODIMM_176", 213 "SODIMM_194", 214 "SODIMM_55", 215 "SODIMM_63", 216 "SODIMM_28", 217 "SODIMM_93", 218 "SODIMM_69", 219 "SODIMM_99", 220 "SODIMM_130", 221 "SODIMM_106", 222 "SODIMM_98", 223 "SODIMM_192", 224 "SODIMM_49", 225 "SODIMM_190", 226 "SODIMM_51", 227 "SODIMM_47", 228 "SODIMM_53", 229 "", 230 "SODIMM_22"; 231}; 232 233&gpio2 { 234 gpio-line-names = "SODIMM_132", 235 "SODIMM_134", 236 "SODIMM_135", 237 "SODIMM_133", 238 "SODIMM_102", 239 "SODIMM_43", 240 "SODIMM_127", 241 "SODIMM_37", 242 "SODIMM_104", 243 "SODIMM_59", 244 "SODIMM_30", 245 "SODIMM_100", 246 "SODIMM_38", 247 "SODIMM_34", 248 "SODIMM_32", 249 "SODIMM_36", 250 "SODIMM_59", 251 "SODIMM_67", 252 "SODIMM_97", 253 "SODIMM_79", 254 "SODIMM_103", 255 "SODIMM_101", 256 "SODIMM_45", 257 "SODIMM_105", 258 "SODIMM_107", 259 "SODIMM_91", 260 "SODIMM_89", 261 "SODIMM_150", 262 "SODIMM_126", 263 "SODIMM_128", 264 "", 265 "SODIMM_94"; 266}; 267 268&gpio3 { 269 gpio-line-names = "SODIMM_111", 270 "SODIMM_113", 271 "SODIMM_115", 272 "SODIMM_117", 273 "SODIMM_119", 274 "SODIMM_121", 275 "SODIMM_123", 276 "SODIMM_125", 277 "SODIMM_110", 278 "SODIMM_112", 279 "SODIMM_114", 280 "SODIMM_116", 281 "SODIMM_118", 282 "SODIMM_120", 283 "SODIMM_122", 284 "SODIMM_124", 285 "", 286 "SODIMM_96", 287 "SODIMM_77", 288 "SODIMM_25", 289 "SODIMM_27", 290 "SODIMM_88", 291 "SODIMM_90", 292 "SODIMM_31", 293 "SODIMM_23", 294 "SODIMM_29", 295 "SODIMM_71", 296 "SODIMM_73", 297 "SODIMM_92", 298 "SODIMM_81", 299 "SODIMM_131", 300 "SODIMM_129"; 301}; 302 303&gpio4 { 304 gpio-line-names = "", 305 "", 306 "", 307 "", 308 "", 309 "SODIMM_168", 310 "", 311 "", 312 "", 313 "", 314 "SODIMM_184", 315 "SODIMM_186", 316 "HDMI_15", 317 "HDMI_16", 318 "SODIMM_178", 319 "SODIMM_188", 320 "SODIMM_56", 321 "SODIMM_44", 322 "SODIMM_68", 323 "SODIMM_82", 324 "SODIMM_24", 325 "SODIMM_76", 326 "SODIMM_70", 327 "SODIMM_60", 328 "SODIMM_58", 329 "SODIMM_78", 330 "SODIMM_72", 331 "SODIMM_80", 332 "SODIMM_46", 333 "SODIMM_62", 334 "SODIMM_48", 335 "SODIMM_74"; 336}; 337 338&gpio5 { 339 gpio-line-names = "SODIMM_95", 340 "", 341 "SODIMM_86", 342 "", 343 "SODIMM_65", 344 "SODIMM_50", 345 "SODIMM_52", 346 "SODIMM_54", 347 "SODIMM_66", 348 "SODIMM_64", 349 "SODIMM_57", 350 "SODIMM_61", 351 "SODIMM_136", 352 "SODIMM_138", 353 "SODIMM_140", 354 "SODIMM_142", 355 "SODIMM_144", 356 "SODIMM_146", 357 "SODIMM_172", 358 "SODIMM_170", 359 "SODIMM_149", 360 "SODIMM_151", 361 "SODIMM_153", 362 "SODIMM_155", 363 "SODIMM_157", 364 "SODIMM_159", 365 "SODIMM_161", 366 "SODIMM_163", 367 "SODIMM_33", 368 "SODIMM_35", 369 "SODIMM_165", 370 "SODIMM_167"; 371}; 372 373&gpio6 { 374 gpio-line-names = "SODIMM_169", 375 "SODIMM_171", 376 "SODIMM_173", 377 "SODIMM_175", 378 "SODIMM_177", 379 "SODIMM_179", 380 "SODIMM_85", 381 "SODIMM_166", 382 "SODIMM_160", 383 "SODIMM_162", 384 "SODIMM_158", 385 "SODIMM_164", 386 "", 387 "", 388 "SODIMM_156", 389 "SODIMM_75", 390 "SODIMM_154", 391 "", 392 "", 393 "", 394 "", 395 "", 396 "", 397 "", 398 "", 399 "", 400 "", 401 "", 402 "", 403 "", 404 "", 405 "SODIMM_152"; 406}; 407 408&gpio7 { 409 gpio-line-names = "", 410 "", 411 "", 412 "", 413 "", 414 "", 415 "", 416 "", 417 "", 418 "SODIMM_19", 419 "SODIMM_21", 420 "", 421 "SODIMM_137"; 422}; 423 424&hdmi { 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pinctrl_hdmi_ddc>; 427 status = "disabled"; 428}; 429 430/* 431 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 432 * touch screen controller 433 */ 434&i2c2 { 435 clock-frequency = <100000>; 436 pinctrl-names = "default", "gpio"; 437 pinctrl-0 = <&pinctrl_i2c2>; 438 pinctrl-1 = <&pinctrl_i2c2_gpio>; 439 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 440 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 441 status = "okay"; 442 443 pmic: pmic@8 { 444 compatible = "fsl,pfuze100"; 445 fsl,pmic-stby-poweroff; 446 reg = <0x08>; 447 448 regulators { 449 sw1a_reg: sw1ab { 450 regulator-always-on; 451 regulator-boot-on; 452 regulator-max-microvolt = <1875000>; 453 regulator-min-microvolt = <300000>; 454 regulator-ramp-delay = <6250>; 455 }; 456 457 sw1c_reg: sw1c { 458 regulator-always-on; 459 regulator-boot-on; 460 regulator-max-microvolt = <1875000>; 461 regulator-min-microvolt = <300000>; 462 regulator-ramp-delay = <6250>; 463 }; 464 465 sw3a_reg: sw3a { 466 regulator-always-on; 467 regulator-boot-on; 468 regulator-max-microvolt = <1975000>; 469 regulator-min-microvolt = <400000>; 470 }; 471 472 swbst_reg: swbst { 473 regulator-always-on; 474 regulator-boot-on; 475 regulator-max-microvolt = <5150000>; 476 regulator-min-microvolt = <5000000>; 477 }; 478 479 snvs_reg: vsnvs { 480 regulator-always-on; 481 regulator-boot-on; 482 regulator-max-microvolt = <3000000>; 483 regulator-min-microvolt = <1000000>; 484 }; 485 486 vref_reg: vrefddr { 487 regulator-always-on; 488 regulator-boot-on; 489 }; 490 491 /* vgen1: unused */ 492 493 vgen2_reg: vgen2 { 494 regulator-always-on; 495 regulator-boot-on; 496 regulator-max-microvolt = <1550000>; 497 regulator-min-microvolt = <800000>; 498 }; 499 500 /* 501 * +V3.3_1.8_SD1 coming off VGEN3 and supplying 502 * the i.MX 6 NVCC_SD1. 503 */ 504 vgen3_reg: vgen3 { 505 regulator-always-on; 506 regulator-boot-on; 507 regulator-max-microvolt = <3300000>; 508 regulator-min-microvolt = <1800000>; 509 }; 510 511 vgen4_reg: vgen4 { 512 regulator-always-on; 513 regulator-boot-on; 514 regulator-max-microvolt = <1800000>; 515 regulator-min-microvolt = <1800000>; 516 }; 517 518 vgen5_reg: vgen5 { 519 regulator-always-on; 520 regulator-boot-on; 521 regulator-max-microvolt = <3300000>; 522 regulator-min-microvolt = <1800000>; 523 }; 524 525 vgen6_reg: vgen6 { 526 regulator-always-on; 527 regulator-boot-on; 528 regulator-max-microvolt = <3300000>; 529 regulator-min-microvolt = <1800000>; 530 }; 531 }; 532 }; 533 534 codec: sgtl5000@a { 535 compatible = "fsl,sgtl5000"; 536 clocks = <&clks IMX6QDL_CLK_CKO>; 537 lrclk-strength = <3>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&pinctrl_sgtl5000>; 540 reg = <0x0a>; 541 #sound-dai-cells = <0>; 542 VDDA-supply = <®_module_3v3_audio>; 543 VDDIO-supply = <®_module_3v3>; 544 VDDD-supply = <&vgen4_reg>; 545 }; 546 547 /* STMPE811 touch screen controller */ 548 stmpe811@41 { 549 compatible = "st,stmpe811"; 550 blocks = <0x5>; 551 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 552 interrupt-parent = <&gpio6>; 553 interrupt-controller; 554 id = <0>; 555 irq-trigger = <0x1>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pinctrl_touch_int>; 558 reg = <0x41>; 559 /* 3.25 MHz ADC clock speed */ 560 st,adc-freq = <1>; 561 /* 12-bit ADC */ 562 st,mod-12b = <1>; 563 /* internal ADC reference */ 564 st,ref-sel = <0>; 565 /* ADC converstion time: 80 clocks */ 566 st,sample-time = <4>; 567 568 stmpe_ts: stmpe_touchscreen { 569 compatible = "st,stmpe-ts"; 570 /* 8 sample average control */ 571 st,ave-ctrl = <3>; 572 /* 7 length fractional part in z */ 573 st,fraction-z = <7>; 574 /* 575 * 50 mA typical 80 mA max touchscreen drivers 576 * current limit value 577 */ 578 st,i-drive = <1>; 579 /* 1 ms panel driver settling time */ 580 st,settling = <3>; 581 /* 5 ms touch detect interrupt delay */ 582 st,touch-det-delay = <5>; 583 status = "disabled"; 584 }; 585 586 stmpe_adc: stmpe_adc { 587 compatible = "st,stmpe-adc"; 588 /* forbid to use ADC channels 3-0 (touch) */ 589 st,norequest-mask = <0x0F>; 590 }; 591 }; 592}; 593 594/* 595 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 596 */ 597&i2c3 { 598 clock-frequency = <100000>; 599 pinctrl-names = "default", "gpio"; 600 pinctrl-0 = <&pinctrl_i2c3>; 601 pinctrl-1 = <&pinctrl_i2c3_gpio>; 602 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 603 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 604 status = "disabled"; 605 606 atmel_mxt_ts: touchscreen@4a { 607 compatible = "atmel,maxtouch"; 608 interrupt-parent = <&gpio2>; 609 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_atmel_conn>; 612 reg = <0x4a>; 613 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ 614 status = "disabled"; 615 }; 616}; 617 618&ipu1_di0_disp0 { 619 remote-endpoint = <&lcd_display_in>; 620}; 621 622/* Colibri PWM<B> */ 623&pwm1 { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_pwm1>; 626 status = "disabled"; 627}; 628 629/* Colibri PWM<D> */ 630&pwm2 { 631 pinctrl-names = "default"; 632 pinctrl-0 = <&pinctrl_pwm2>; 633 status = "disabled"; 634}; 635 636/* Colibri PWM<A> */ 637&pwm3 { 638 pinctrl-names = "default"; 639 pinctrl-0 = <&pinctrl_pwm3>; 640 status = "disabled"; 641}; 642 643/* Colibri PWM<C> */ 644&pwm4 { 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pinctrl_pwm4>; 647 status = "disabled"; 648}; 649 650/* Optional S/PDIF out on SODIMM 137 */ 651&spdif { 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_spdif>; 654 status = "disabled"; 655}; 656 657&ssi1 { 658 status = "okay"; 659}; 660 661/* Colibri UART_A */ 662&uart1 { 663 fsl,dte-mode; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 666 uart-has-rtscts; 667 status = "disabled"; 668}; 669 670/* Colibri UART_B */ 671&uart2 { 672 fsl,dte-mode; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&pinctrl_uart2_dte>; 675 uart-has-rtscts; 676 status = "disabled"; 677}; 678 679/* Colibri UART_C */ 680&uart3 { 681 fsl,dte-mode; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&pinctrl_uart3_dte>; 684 status = "disabled"; 685}; 686 687/* Colibri USBH */ 688&usbh1 { 689 vbus-supply = <®_usb_host_vbus>; 690}; 691 692/* Colibri USBC */ 693&usbotg { 694 dr_mode = "otg"; 695 extcon = <0>, <&extcon_usbc_det>; 696 status = "disabled"; 697}; 698 699/* Colibri MMC */ 700&usdhc1 { 701 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ 702 bus-width = <4>; 703 no-1-8-v; 704 disable-wp; 705 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 706 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; 707 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; 708 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; 709 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; 710 vmmc-supply = <®_module_3v3>; 711 vqmmc-supply = <&vgen3_reg>; 712 status = "disabled"; 713}; 714 715/* eMMC */ 716&usdhc3 { 717 bus-width = <8>; 718 no-1-8-v; 719 non-removable; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&pinctrl_usdhc3>; 722 vqmmc-supply = <®_module_3v3>; 723 status = "okay"; 724}; 725 726&weim { 727 pinctrl-names = "default"; 728 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 729 &pinctrl_weim_cs1 &pinctrl_weim_cs2 730 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; 731 #address-cells = <2>; 732 #size-cells = <1>; 733 status = "disabled"; 734}; 735 736&iomuxc { 737 pinctrl-names = "default"; 738 pinctrl-0 = <&pinctrl_usbh_oc_1>; 739 740 /* Atmel MXT touchsceen + Capacitive Touch Adapter */ 741 /* NOTE: This pin group conflicts with pin groups 742 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. 743 */ 744 pinctrl_atmel_adap: atmeladaptergrp { 745 fsl,pins = < 746 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ 747 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ 748 >; 749 }; 750 751 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ 752 /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and 753 * pinctrl_weim_cs2. Don't use them simultaneously. 754 */ 755 pinctrl_atmel_conn: atmelconnectorgrp { 756 fsl,pins = < 757 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ 758 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ 759 >; 760 }; 761 762 pinctrl_audmux: audmuxgrp { 763 fsl,pins = < 764 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 765 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 766 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 767 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 768 >; 769 }; 770 771 pinctrl_cam_mclk: cammclkgrp { 772 fsl,pins = < 773 /* Parallel Camera CAM sys_mclk */ 774 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 775 >; 776 }; 777 778 /* CSI pins used as GPIOs */ 779 pinctrl_csi_gpio_1: csigpio1grp { 780 fsl,pins = < 781 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 782 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 783 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 784 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 785 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 786 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 787 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 788 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 789 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 790 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 791 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 792 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 793 >; 794 }; 795 796 pinctrl_csi_gpio_2: csigpio2grp { 797 fsl,pins = < 798 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 799 >; 800 }; 801 802 pinctrl_ecspi4: ecspi4grp { 803 fsl,pins = < 804 /* SPI CS */ 805 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 806 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 807 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 808 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 809 >; 810 }; 811 812 pinctrl_enet: enetgrp { 813 fsl,pins = < 814 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 815 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 816 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 817 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 818 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 819 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 820 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 821 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 822 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 823 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) 824 >; 825 }; 826 827 pinctrl_flexcan1: flexcan1grp { 828 fsl,pins = < 829 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 830 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 831 >; 832 }; 833 834 pinctrl_flexcan2: flexcan2grp { 835 fsl,pins = < 836 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 837 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 838 >; 839 }; 840 841 pinctrl_gpio_1: gpio1grp { 842 fsl,pins = < 843 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 844 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 845 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 846 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 847 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 848 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 849 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 850 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 851 >; 852 }; 853 pinctrl_gpio_2: gpio2grp { 854 fsl,pins = < 855 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 856 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 857 >; 858 }; 859 860 pinctrl_gpio_bl_on: gpioblongrp { 861 fsl,pins = < 862 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 863 >; 864 }; 865 866 pinctrl_gpio_keys: gpiokeysgrp { 867 fsl,pins = < 868 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 869 >; 870 }; 871 872 pinctrl_hdmi_ddc: hdmiddcgrp { 873 fsl,pins = < 874 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 875 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 876 >; 877 }; 878 879 pinctrl_i2c2: i2c2grp { 880 fsl,pins = < 881 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 882 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 883 >; 884 }; 885 886 pinctrl_i2c2_gpio: i2c2gpiogrp { 887 fsl,pins = < 888 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 889 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 890 >; 891 }; 892 893 pinctrl_i2c3: i2c3grp { 894 fsl,pins = < 895 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 896 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 897 >; 898 }; 899 900 pinctrl_i2c3_gpio: i2c3gpiogrp { 901 fsl,pins = < 902 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 903 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 904 >; 905 }; 906 907 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ 908 fsl,pins = < 909 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 910 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 911 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 912 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 913 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 914 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 915 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 916 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 917 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 918 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 919 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 920 /* Disable PWM pins on camera interface */ 921 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 922 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 923 >; 924 }; 925 926 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 927 fsl,pins = < 928 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 929 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 930 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 931 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 932 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 933 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 934 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 935 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 936 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 937 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 938 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 939 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 940 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 941 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 942 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 943 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 944 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 945 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 946 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 947 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 948 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 949 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 950 >; 951 }; 952 953 pinctrl_lvds_transceiver: lvdstxgrp { 954 fsl,pins = < 955 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ 956 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ 957 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ 958 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ 959 >; 960 }; 961 962 pinctrl_mic_gnd: micgndgrp { 963 fsl,pins = < 964 /* Controls Mic GND, PU or '1' pull Mic GND to GND */ 965 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 966 >; 967 }; 968 969 pinctrl_mmc_cd: mmccdgrp { 970 fsl,pins = < 971 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 972 >; 973 }; 974 975 pinctrl_mmc_cd_sleep: mmccdslpgrp { 976 fsl,pins = < 977 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 978 >; 979 }; 980 981 pinctrl_pwm1: pwm1grp { 982 fsl,pins = < 983 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 984 >; 985 }; 986 987 pinctrl_pwm2: pwm2grp { 988 fsl,pins = < 989 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 990 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 991 >; 992 }; 993 994 pinctrl_pwm3: pwm3grp { 995 fsl,pins = < 996 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 997 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 998 >; 999 }; 1000 1001 pinctrl_pwm4: pwm4grp { 1002 fsl,pins = < 1003 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 1004 >; 1005 }; 1006 1007 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 1008 fsl,pins = < 1009 /* SODIMM 129 / USBH_PEN */ 1010 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 1011 >; 1012 }; 1013 1014 pinctrl_sgtl5000: sgtl5000grp { 1015 fsl,pins = < 1016 /* SGTL5000 sys_mclk */ 1017 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 1018 >; 1019 }; 1020 1021 pinctrl_spdif: spdifgrp { 1022 fsl,pins = < 1023 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1024 >; 1025 }; 1026 1027 pinctrl_touch_int: gpiotouchintgrp { 1028 fsl,pins = < 1029 /* STMPE811 interrupt */ 1030 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 1031 >; 1032 }; 1033 1034 pinctrl_uart1_dce: uart1dcegrp { 1035 fsl,pins = < 1036 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1037 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1038 >; 1039 }; 1040 1041 /* DTE mode */ 1042 pinctrl_uart1_dte: uart1dtegrp { 1043 fsl,pins = < 1044 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1045 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1046 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1047 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1048 >; 1049 }; 1050 1051 /* Additional DTR, DSR, DCD */ 1052 pinctrl_uart1_ctrl: uart1ctrlgrp { 1053 fsl,pins = < 1054 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1055 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1056 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1057 >; 1058 }; 1059 1060 pinctrl_uart2_dte: uart2dtegrp { 1061 fsl,pins = < 1062 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1063 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1064 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1065 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1066 >; 1067 }; 1068 1069 pinctrl_uart3_dte: uart3dtegrp { 1070 fsl,pins = < 1071 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 1072 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 1073 >; 1074 }; 1075 1076 pinctrl_usbc_det: usbcdetgrp { 1077 fsl,pins = < 1078 /* SODIMM 137 / USBC_DET */ 1079 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 1080 /* USBC_DET_OVERWRITE */ 1081 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 1082 /* USBC_DET_EN */ 1083 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 1084 >; 1085 }; 1086 1087 pinctrl_usbc_id_1: usbcid1grp { 1088 fsl,pins = < 1089 /* USBC_ID */ 1090 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 1091 >; 1092 }; 1093 1094 pinctrl_usbh_oc_1: usbhoc1grp { 1095 fsl,pins = < 1096 /* USBH_OC */ 1097 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 1098 >; 1099 }; 1100 1101 pinctrl_usdhc1: usdhc1grp { 1102 fsl,pins = < 1103 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1104 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1105 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1106 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1107 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1108 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1109 >; 1110 }; 1111 1112 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1113 fsl,pins = < 1114 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 1115 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 1116 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 1117 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 1118 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 1119 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 1120 >; 1121 }; 1122 1123 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1124 fsl,pins = < 1125 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 1126 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 1127 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 1128 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 1129 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 1130 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 1131 >; 1132 }; 1133 1134 /* avoid backfeeding with removed card power */ 1135 pinctrl_usdhc1_sleep: usdhc1sleepgrp { 1136 fsl,pins = < 1137 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 1138 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 1139 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 1140 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 1141 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 1142 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 1143 >; 1144 }; 1145 1146 pinctrl_usdhc3: usdhc3grp { 1147 fsl,pins = < 1148 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1149 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1150 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1151 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1152 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1153 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1154 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1155 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1156 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1157 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1158 /* eMMC reset */ 1159 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1160 >; 1161 }; 1162 1163 pinctrl_weim_cs0: weimcs0grp { 1164 fsl,pins = < 1165 /* nEXT_CS0 */ 1166 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1167 >; 1168 }; 1169 1170 pinctrl_weim_cs1: weimcs1grp { 1171 fsl,pins = < 1172 /* nEXT_CS1 */ 1173 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 1174 >; 1175 }; 1176 1177 pinctrl_weim_cs2: weimcs2grp { 1178 fsl,pins = < 1179 /* nEXT_CS2 */ 1180 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 1181 >; 1182 }; 1183 1184 /* ADDRESS[16:18] [25] used as GPIO */ 1185 pinctrl_weim_gpio_1: weimgpio1grp { 1186 fsl,pins = < 1187 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1188 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1189 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1190 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1191 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1192 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1193 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1194 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1195 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1196 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1197 >; 1198 }; 1199 1200 /* ADDRESS[19:24] used as GPIO */ 1201 pinctrl_weim_gpio_2: weimgpio2grp { 1202 fsl,pins = < 1203 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1204 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1205 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1206 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1207 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1208 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1209 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1210 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1211 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1212 >; 1213 }; 1214 1215 /* DATA[16:31] used as GPIO */ 1216 pinctrl_weim_gpio_3: weimgpio3grp { 1217 fsl,pins = < 1218 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 1219 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 1220 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 1221 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 1222 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 1223 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1224 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 1225 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 1226 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 1227 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 1228 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 1229 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 1230 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 1231 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 1232 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 1233 >; 1234 }; 1235 1236 /* DQM[0:3] used as GPIO */ 1237 pinctrl_weim_gpio_4: weimgpio4grp { 1238 fsl,pins = < 1239 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 1240 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 1241 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 1242 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 1243 >; 1244 }; 1245 1246 /* RDY used as GPIO */ 1247 pinctrl_weim_gpio_5: weimgpio5grp { 1248 fsl,pins = < 1249 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 1250 >; 1251 }; 1252 1253 /* ADDRESS[16] DATA[30] used as GPIO */ 1254 pinctrl_weim_gpio_6: weimgpio6grp { 1255 fsl,pins = < 1256 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 1257 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1258 >; 1259 }; 1260 1261 pinctrl_weim_npwe: weimnpwegrp { 1262 fsl,pins = < 1263 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 1264 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 1265 >; 1266 }; 1267 1268 pinctrl_weim_sram: weimsramgrp { 1269 fsl,pins = < 1270 /* Data */ 1271 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 1272 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 1273 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 1274 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 1275 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 1276 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 1277 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 1278 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 1279 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 1280 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 1281 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 1282 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 1283 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 1284 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 1285 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 1286 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 1287 /* Address */ 1288 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1289 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1290 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1291 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1292 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1293 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1294 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1295 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1296 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1297 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1298 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1299 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1300 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1301 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1302 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1303 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1304 /* Ctrl */ 1305 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1306 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1307 >; 1308 }; 1309 1310 pinctrl_weim_rdnwr: weimrdnwrgrp { 1311 fsl,pins = < 1312 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 1313 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 1314 >; 1315 }; 1316}; 1317