1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-msm8974.h> 10#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/reset/qcom,gcc-msm8974.h> 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 interrupt-parent = <&intc>; 20 21 chosen { }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0x0 0x0>; 26 }; 27 28 clocks { 29 xo_board: xo_board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <19200000>; 33 }; 34 35 sleep_clk: sleep_clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32768>; 39 }; 40 }; 41 42 firmware { 43 scm { 44 compatible = "qcom,scm-msm8226", "qcom,scm"; 45 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 46 clock-names = "core", "bus", "iface"; 47 }; 48 }; 49 50 pmu { 51 compatible = "arm,cortex-a7-pmu"; 52 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 53 IRQ_TYPE_LEVEL_HIGH)>; 54 }; 55 56 rpm: remoteproc { 57 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; 58 59 master-stats { 60 compatible = "qcom,rpm-master-stats"; 61 qcom,rpm-msg-ram = <&apss_master_stats>, 62 <&mpss_master_stats>, 63 <&lpss_master_stats>, 64 <&pronto_master_stats>; 65 qcom,master-names = "APSS", 66 "MPSS", 67 "LPSS", 68 "PRONTO"; 69 }; 70 71 smd-edge { 72 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 73 qcom,ipc = <&apcs 8 0>; 74 qcom,smd-edge = <15>; 75 76 rpm_requests: rpm-requests { 77 compatible = "qcom,rpm-msm8226"; 78 qcom,smd-channels = "rpm_requests"; 79 80 rpmcc: clock-controller { 81 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; 82 #clock-cells = <1>; 83 clocks = <&xo_board>; 84 clock-names = "xo"; 85 }; 86 87 rpmpd: power-controller { 88 compatible = "qcom,msm8226-rpmpd"; 89 #power-domain-cells = <1>; 90 operating-points-v2 = <&rpmpd_opp_table>; 91 92 rpmpd_opp_table: opp-table { 93 compatible = "operating-points-v2"; 94 95 rpmpd_opp_ret: opp1 { 96 opp-level = <1>; 97 }; 98 rpmpd_opp_svs_krait: opp2 { 99 opp-level = <2>; 100 }; 101 rpmpd_opp_svs_soc: opp3 { 102 opp-level = <3>; 103 }; 104 rpmpd_opp_nom: opp4 { 105 opp-level = <4>; 106 }; 107 rpmpd_opp_turbo: opp5 { 108 opp-level = <5>; 109 }; 110 rpmpd_opp_super_turbo: opp6 { 111 opp-level = <6>; 112 }; 113 }; 114 }; 115 }; 116 }; 117 }; 118 119 reserved-memory { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 124 smem_region: smem@3000000 { 125 reg = <0x3000000 0x100000>; 126 no-map; 127 }; 128 129 adsp_region: adsp@dc00000 { 130 reg = <0x0dc00000 0x1900000>; 131 no-map; 132 }; 133 }; 134 135 smem { 136 compatible = "qcom,smem"; 137 138 memory-region = <&smem_region>; 139 qcom,rpm-msg-ram = <&rpm_msg_ram>; 140 141 hwlocks = <&tcsr_mutex 3>; 142 }; 143 144 smp2p-adsp { 145 compatible = "qcom,smp2p"; 146 qcom,smem = <443>, <429>; 147 148 interrupt-parent = <&intc>; 149 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 150 151 qcom,ipc = <&apcs 8 10>; 152 153 qcom,local-pid = <0>; 154 qcom,remote-pid = <2>; 155 156 adsp_smp2p_out: master-kernel { 157 qcom,entry-name = "master-kernel"; 158 #qcom,smem-state-cells = <1>; 159 }; 160 161 adsp_smp2p_in: slave-kernel { 162 qcom,entry-name = "slave-kernel"; 163 164 interrupt-controller; 165 #interrupt-cells = <2>; 166 }; 167 }; 168 169 soc: soc { 170 compatible = "simple-bus"; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges; 174 175 intc: interrupt-controller@f9000000 { 176 compatible = "qcom,msm-qgic2"; 177 reg = <0xf9000000 0x1000>, 178 <0xf9002000 0x1000>; 179 interrupt-controller; 180 #interrupt-cells = <3>; 181 }; 182 183 apcs: syscon@f9011000 { 184 compatible = "syscon"; 185 reg = <0xf9011000 0x1000>; 186 }; 187 188 sdhc_1: mmc@f9824900 { 189 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 190 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 191 reg-names = "hc", "core"; 192 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "hc_irq", "pwr_irq"; 195 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 196 <&gcc GCC_SDCC1_APPS_CLK>, 197 <&rpmcc RPM_SMD_XO_CLK_SRC>; 198 clock-names = "iface", "core", "xo"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&sdhc1_default_state>; 201 status = "disabled"; 202 }; 203 204 sdhc_2: mmc@f98a4900 { 205 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 206 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 207 reg-names = "hc", "core"; 208 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "hc_irq", "pwr_irq"; 211 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 212 <&gcc GCC_SDCC2_APPS_CLK>, 213 <&rpmcc RPM_SMD_XO_CLK_SRC>; 214 clock-names = "iface", "core", "xo"; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&sdhc2_default_state>; 217 status = "disabled"; 218 }; 219 220 sdhc_3: mmc@f9864900 { 221 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 222 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 223 reg-names = "hc", "core"; 224 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "hc_irq", "pwr_irq"; 227 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 228 <&gcc GCC_SDCC3_APPS_CLK>, 229 <&rpmcc RPM_SMD_XO_CLK_SRC>; 230 clock-names = "iface", "core", "xo"; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&sdhc3_default_state>; 233 status = "disabled"; 234 }; 235 236 blsp1_uart1: serial@f991d000 { 237 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 238 reg = <0xf991d000 0x1000>; 239 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 241 clock-names = "core", "iface"; 242 status = "disabled"; 243 }; 244 245 blsp1_uart2: serial@f991e000 { 246 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 247 reg = <0xf991e000 0x1000>; 248 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 250 <&gcc GCC_BLSP1_AHB_CLK>; 251 clock-names = "core", 252 "iface"; 253 status = "disabled"; 254 }; 255 256 blsp1_uart3: serial@f991f000 { 257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 258 reg = <0xf991f000 0x1000>; 259 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 261 clock-names = "core", "iface"; 262 status = "disabled"; 263 }; 264 265 blsp1_uart4: serial@f9920000 { 266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 267 reg = <0xf9920000 0x1000>; 268 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 270 clock-names = "core", "iface"; 271 status = "disabled"; 272 }; 273 274 blsp1_i2c1: i2c@f9923000 { 275 status = "disabled"; 276 compatible = "qcom,i2c-qup-v2.1.1"; 277 reg = <0xf9923000 0x1000>; 278 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 280 clock-names = "core", "iface"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&blsp1_i2c1_pins>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 }; 286 287 blsp1_i2c2: i2c@f9924000 { 288 status = "disabled"; 289 compatible = "qcom,i2c-qup-v2.1.1"; 290 reg = <0xf9924000 0x1000>; 291 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 293 clock-names = "core", "iface"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&blsp1_i2c2_pins>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 }; 299 300 blsp1_i2c3: i2c@f9925000 { 301 status = "disabled"; 302 compatible = "qcom,i2c-qup-v2.1.1"; 303 reg = <0xf9925000 0x1000>; 304 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 306 clock-names = "core", "iface"; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&blsp1_i2c3_pins>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 }; 312 313 blsp1_i2c4: i2c@f9926000 { 314 status = "disabled"; 315 compatible = "qcom,i2c-qup-v2.1.1"; 316 reg = <0xf9926000 0x1000>; 317 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 319 clock-names = "core", "iface"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&blsp1_i2c4_pins>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 }; 325 326 blsp1_i2c5: i2c@f9927000 { 327 status = "disabled"; 328 compatible = "qcom,i2c-qup-v2.1.1"; 329 reg = <0xf9927000 0x1000>; 330 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 332 clock-names = "core", "iface"; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&blsp1_i2c5_pins>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 }; 338 339 blsp1_i2c6: i2c@f9928000 { 340 compatible = "qcom,i2c-qup-v2.1.1"; 341 reg = <0xf9928000 0x1000>; 342 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 344 <&gcc GCC_BLSP1_AHB_CLK>; 345 clock-names = "core", 346 "iface"; 347 pinctrl-0 = <&blsp1_i2c6_pins>; 348 pinctrl-names = "default"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 status = "disabled"; 352 }; 353 354 cci: cci@fda0c000 { 355 compatible = "qcom,msm8226-cci"; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 reg = <0xfda0c000 0x1000>; 359 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 360 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 361 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 362 <&mmcc CAMSS_CCI_CCI_CLK>; 363 clock-names = "camss_top_ahb", 364 "cci_ahb", 365 "cci"; 366 367 pinctrl-names = "default", "sleep"; 368 pinctrl-0 = <&cci_default>; 369 pinctrl-1 = <&cci_sleep>; 370 371 status = "disabled"; 372 373 cci_i2c0: i2c-bus@0 { 374 reg = <0>; 375 clock-frequency = <400000>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 }; 379 }; 380 381 usb: usb@f9a55000 { 382 compatible = "qcom,ci-hdrc"; 383 reg = <0xf9a55000 0x200>, 384 <0xf9a55200 0x200>; 385 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 387 <&gcc GCC_USB_HS_SYSTEM_CLK>; 388 clock-names = "iface", "core"; 389 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 390 assigned-clock-rates = <75000000>; 391 resets = <&gcc GCC_USB_HS_BCR>; 392 reset-names = "core"; 393 phy_type = "ulpi"; 394 dr_mode = "otg"; 395 hnp-disable; 396 srp-disable; 397 adp-disable; 398 ahb-burst-config = <0>; 399 phy-names = "usb-phy"; 400 phys = <&usb_hs_phy>; 401 status = "disabled"; 402 #reset-cells = <1>; 403 404 ulpi { 405 usb_hs_phy: phy { 406 compatible = "qcom,usb-hs-phy-msm8226", 407 "qcom,usb-hs-phy"; 408 #phy-cells = <0>; 409 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 410 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 411 clock-names = "ref", "sleep"; 412 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 413 reset-names = "phy", "por"; 414 qcom,init-seq = /bits/ 8 <0x0 0x44 415 0x1 0x68 0x2 0x24 0x3 0x13>; 416 }; 417 }; 418 }; 419 420 gcc: clock-controller@fc400000 { 421 compatible = "qcom,gcc-msm8226"; 422 reg = <0xfc400000 0x4000>; 423 #clock-cells = <1>; 424 #reset-cells = <1>; 425 #power-domain-cells = <1>; 426 427 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 428 <&sleep_clk>; 429 clock-names = "xo", 430 "sleep_clk"; 431 }; 432 433 mmcc: clock-controller@fd8c0000 { 434 compatible = "qcom,mmcc-msm8226"; 435 reg = <0xfd8c0000 0x6000>; 436 #clock-cells = <1>; 437 #reset-cells = <1>; 438 #power-domain-cells = <1>; 439 440 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 441 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 442 <&gcc GPLL0_VOTE>, 443 <&gcc GPLL1_VOTE>, 444 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 445 <0>, 446 <0>; 447 clock-names = "xo", 448 "mmss_gpll0_vote", 449 "gpll0_vote", 450 "gpll1_vote", 451 "gfx3d_clk_src", 452 "dsi0pll", 453 "dsi0pllbyte"; 454 }; 455 456 tlmm: pinctrl@fd510000 { 457 compatible = "qcom,msm8226-pinctrl"; 458 reg = <0xfd510000 0x4000>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 gpio-ranges = <&tlmm 0 0 117>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 465 466 blsp1_i2c1_pins: blsp1-i2c1-state { 467 pins = "gpio2", "gpio3"; 468 function = "blsp_i2c1"; 469 drive-strength = <2>; 470 bias-disable; 471 }; 472 473 blsp1_i2c2_pins: blsp1-i2c2-state { 474 pins = "gpio6", "gpio7"; 475 function = "blsp_i2c2"; 476 drive-strength = <2>; 477 bias-disable; 478 }; 479 480 blsp1_i2c3_pins: blsp1-i2c3-state { 481 pins = "gpio10", "gpio11"; 482 function = "blsp_i2c3"; 483 drive-strength = <2>; 484 bias-disable; 485 }; 486 487 blsp1_i2c4_pins: blsp1-i2c4-state { 488 pins = "gpio14", "gpio15"; 489 function = "blsp_i2c4"; 490 drive-strength = <2>; 491 bias-disable; 492 }; 493 494 blsp1_i2c5_pins: blsp1-i2c5-state { 495 pins = "gpio18", "gpio19"; 496 function = "blsp_i2c5"; 497 drive-strength = <2>; 498 bias-disable; 499 }; 500 501 blsp1_i2c6_pins: blsp1-i2c6-state { 502 pins = "gpio22", "gpio23"; 503 function = "blsp_i2c6"; 504 drive-strength = <2>; 505 bias-disable; 506 }; 507 508 cci_default: cci-default-state { 509 pins = "gpio29", "gpio30"; 510 function = "cci_i2c0"; 511 512 drive-strength = <2>; 513 bias-disable; 514 }; 515 516 cci_sleep: cci-sleep-state { 517 pins = "gpio29", "gpio30"; 518 function = "gpio"; 519 520 drive-strength = <2>; 521 bias-disable; 522 }; 523 524 sdhc1_default_state: sdhc1-default-state { 525 clk-pins { 526 pins = "sdc1_clk"; 527 drive-strength = <10>; 528 bias-disable; 529 }; 530 531 cmd-data-pins { 532 pins = "sdc1_cmd", "sdc1_data"; 533 drive-strength = <10>; 534 bias-pull-up; 535 }; 536 }; 537 538 sdhc2_default_state: sdhc2-default-state { 539 clk-pins { 540 pins = "sdc2_clk"; 541 drive-strength = <10>; 542 bias-disable; 543 }; 544 545 cmd-data-pins { 546 pins = "sdc2_cmd", "sdc2_data"; 547 drive-strength = <10>; 548 bias-pull-up; 549 }; 550 }; 551 552 sdhc3_default_state: sdhc3-default-state { 553 clk-pins { 554 pins = "gpio44"; 555 function = "sdc3"; 556 drive-strength = <8>; 557 bias-disable; 558 }; 559 560 cmd-pins { 561 pins = "gpio43"; 562 function = "sdc3"; 563 drive-strength = <8>; 564 bias-pull-up; 565 }; 566 567 data-pins { 568 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 569 function = "sdc3"; 570 drive-strength = <8>; 571 bias-pull-up; 572 }; 573 }; 574 }; 575 576 tsens: thermal-sensor@fc4a9000 { 577 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; 578 reg = <0xfc4a9000 0x1000>, /* TM */ 579 <0xfc4a8000 0x1000>; /* SROT */ 580 nvmem-cells = <&tsens_mode>, 581 <&tsens_base1>, <&tsens_base2>, 582 <&tsens_s0_p1>, <&tsens_s0_p2>, 583 <&tsens_s1_p1>, <&tsens_s1_p2>, 584 <&tsens_s2_p1>, <&tsens_s2_p2>, 585 <&tsens_s3_p1>, <&tsens_s3_p2>, 586 <&tsens_s4_p1>, <&tsens_s4_p2>, 587 <&tsens_s5_p1>, <&tsens_s5_p2>, 588 <&tsens_s6_p1>, <&tsens_s6_p2>; 589 nvmem-cell-names = "mode", 590 "base1", "base2", 591 "s0_p1", "s0_p2", 592 "s1_p1", "s1_p2", 593 "s2_p1", "s2_p2", 594 "s3_p1", "s3_p2", 595 "s4_p1", "s4_p2", 596 "s5_p1", "s5_p2", 597 "s6_p1", "s6_p2"; 598 #qcom,sensors = <6>; 599 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 600 interrupt-names = "uplow"; 601 #thermal-sensor-cells = <1>; 602 }; 603 604 restart@fc4ab000 { 605 compatible = "qcom,pshold"; 606 reg = <0xfc4ab000 0x4>; 607 }; 608 609 qfprom: qfprom@fc4bc000 { 610 compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; 611 reg = <0xfc4bc000 0x1000>; 612 #address-cells = <1>; 613 #size-cells = <1>; 614 615 tsens_base1: base1@1c1 { 616 reg = <0x1c1 0x2>; 617 bits = <5 8>; 618 }; 619 620 tsens_s0_p1: s0-p1@1c2 { 621 reg = <0x1c2 0x2>; 622 bits = <5 6>; 623 }; 624 625 tsens_s1_p1: s1-p1@1c4 { 626 reg = <0x1c4 0x1>; 627 bits = <0 6>; 628 }; 629 630 tsens_s2_p1: s2-p1@1c4 { 631 reg = <0x1c4 0x2>; 632 bits = <6 6>; 633 }; 634 635 tsens_s3_p1: s3-p1@1c5 { 636 reg = <0x1c5 0x2>; 637 bits = <4 6>; 638 }; 639 640 tsens_s4_p1: s4-p1@1c6 { 641 reg = <0x1c6 0x1>; 642 bits = <2 6>; 643 }; 644 645 tsens_s5_p1: s5-p1@1c7 { 646 reg = <0x1c7 0x1>; 647 bits = <0 6>; 648 }; 649 650 tsens_s6_p1: s6-p1@1ca { 651 reg = <0x1ca 0x2>; 652 bits = <4 6>; 653 }; 654 655 tsens_base2: base2@1cc { 656 reg = <0x1cc 0x1>; 657 bits = <0 8>; 658 }; 659 660 tsens_s0_p2: s0-p2@1cd { 661 reg = <0x1cd 0x1>; 662 bits = <0 6>; 663 }; 664 665 tsens_s1_p2: s1-p2@1cd { 666 reg = <0x1cd 0x2>; 667 bits = <6 6>; 668 }; 669 670 tsens_s2_p2: s2-p2@1ce { 671 reg = <0x1ce 0x2>; 672 bits = <4 6>; 673 }; 674 675 tsens_s3_p2: s3-p2@1cf { 676 reg = <0x1cf 0x1>; 677 bits = <2 6>; 678 }; 679 680 tsens_s4_p2: s4-p2@446 { 681 reg = <0x446 0x2>; 682 bits = <4 6>; 683 }; 684 685 tsens_s5_p2: s5-p2@447 { 686 reg = <0x447 0x1>; 687 bits = <2 6>; 688 }; 689 690 tsens_s6_p2: s6-p2@44e { 691 reg = <0x44e 0x1>; 692 bits = <1 6>; 693 }; 694 695 tsens_mode: mode@44f { 696 reg = <0x44f 0x1>; 697 bits = <5 3>; 698 }; 699 }; 700 701 spmi_bus: spmi@fc4cf000 { 702 compatible = "qcom,spmi-pmic-arb"; 703 reg-names = "core", "intr", "cnfg"; 704 reg = <0xfc4cf000 0x1000>, 705 <0xfc4cb000 0x1000>, 706 <0xfc4ca000 0x1000>; 707 interrupt-names = "periph_irq"; 708 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 709 qcom,ee = <0>; 710 qcom,channel = <0>; 711 #address-cells = <2>; 712 #size-cells = <0>; 713 interrupt-controller; 714 #interrupt-cells = <4>; 715 }; 716 717 rng@f9bff000 { 718 compatible = "qcom,prng"; 719 reg = <0xf9bff000 0x200>; 720 clocks = <&gcc GCC_PRNG_AHB_CLK>; 721 clock-names = "core"; 722 }; 723 724 timer@f9020000 { 725 compatible = "arm,armv7-timer-mem"; 726 reg = <0xf9020000 0x1000>; 727 #address-cells = <1>; 728 #size-cells = <1>; 729 ranges; 730 731 frame@f9021000 { 732 frame-number = <0>; 733 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 735 reg = <0xf9021000 0x1000>, 736 <0xf9022000 0x1000>; 737 }; 738 739 frame@f9023000 { 740 frame-number = <1>; 741 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 742 reg = <0xf9023000 0x1000>; 743 status = "disabled"; 744 }; 745 746 frame@f9024000 { 747 frame-number = <2>; 748 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 749 reg = <0xf9024000 0x1000>; 750 status = "disabled"; 751 }; 752 753 frame@f9025000 { 754 frame-number = <3>; 755 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 756 reg = <0xf9025000 0x1000>; 757 status = "disabled"; 758 }; 759 760 frame@f9026000 { 761 frame-number = <4>; 762 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 763 reg = <0xf9026000 0x1000>; 764 status = "disabled"; 765 }; 766 767 frame@f9027000 { 768 frame-number = <5>; 769 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 770 reg = <0xf9027000 0x1000>; 771 status = "disabled"; 772 }; 773 774 frame@f9028000 { 775 frame-number = <6>; 776 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 777 reg = <0xf9028000 0x1000>; 778 status = "disabled"; 779 }; 780 }; 781 782 sram@fc190000 { 783 compatible = "qcom,msm8226-rpm-stats"; 784 reg = <0xfc190000 0x10000>; 785 }; 786 787 rpm_msg_ram: sram@fc428000 { 788 compatible = "qcom,rpm-msg-ram"; 789 reg = <0xfc428000 0x4000>; 790 791 #address-cells = <1>; 792 #size-cells = <1>; 793 ranges = <0 0xfc428000 0x4000>; 794 795 apss_master_stats: sram@150 { 796 reg = <0x150 0x14>; 797 }; 798 799 mpss_master_stats: sram@b50 { 800 reg = <0xb50 0x14>; 801 }; 802 803 lpss_master_stats: sram@1550 { 804 reg = <0x1550 0x14>; 805 }; 806 807 pronto_master_stats: sram@1f50 { 808 reg = <0x1f50 0x14>; 809 }; 810 }; 811 812 tcsr_mutex: hwlock@fd484000 { 813 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; 814 reg = <0xfd484000 0x1000>; 815 #hwlock-cells = <1>; 816 }; 817 818 adsp: remoteproc@fe200000 { 819 compatible = "qcom,msm8226-adsp-pil"; 820 reg = <0xfe200000 0x100>; 821 822 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 823 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 824 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 825 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 826 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 827 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 828 829 power-domains = <&rpmpd MSM8226_VDDCX>; 830 power-domain-names = "cx"; 831 832 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 833 clock-names = "xo"; 834 835 memory-region = <&adsp_region>; 836 837 qcom,smem-states = <&adsp_smp2p_out 0>; 838 qcom,smem-state-names = "stop"; 839 840 status = "disabled"; 841 842 smd-edge { 843 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 844 845 qcom,ipc = <&apcs 8 8>; 846 qcom,smd-edge = <1>; 847 848 label = "lpass"; 849 }; 850 }; 851 852 sram@fdd00000 { 853 compatible = "qcom,msm8226-ocmem"; 854 reg = <0xfdd00000 0x2000>, 855 <0xfec00000 0x20000>; 856 reg-names = "ctrl", "mem"; 857 ranges = <0 0xfec00000 0x20000>; 858 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; 859 clock-names = "core"; 860 861 #address-cells = <1>; 862 #size-cells = <1>; 863 864 gmu_sram: gmu-sram@0 { 865 reg = <0x0 0x20000>; 866 }; 867 }; 868 869 sram@fe805000 { 870 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 871 reg = <0xfe805000 0x1000>; 872 873 reboot-mode { 874 compatible = "syscon-reboot-mode"; 875 offset = <0x65c>; 876 877 mode-bootloader = <0x77665500>; 878 mode-normal = <0x77665501>; 879 mode-recovery = <0x77665502>; 880 }; 881 }; 882 883 mdss: display-subsystem@fd900000 { 884 compatible = "qcom,mdss"; 885 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 886 reg-names = "mdss_phys", "vbif_phys"; 887 888 power-domains = <&mmcc MDSS_GDSC>; 889 890 clocks = <&mmcc MDSS_AHB_CLK>, 891 <&mmcc MDSS_AXI_CLK>, 892 <&mmcc MDSS_VSYNC_CLK>; 893 clock-names = "iface", 894 "bus", 895 "vsync"; 896 897 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 898 899 interrupt-controller; 900 #interrupt-cells = <1>; 901 902 #address-cells = <1>; 903 #size-cells = <1>; 904 ranges; 905 906 status = "disabled"; 907 908 mdss_mdp: display-controller@fd900000 { 909 compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; 910 reg = <0xfd900100 0x22000>; 911 reg-names = "mdp_phys"; 912 913 interrupt-parent = <&mdss>; 914 interrupts = <0>; 915 916 clocks = <&mmcc MDSS_AHB_CLK>, 917 <&mmcc MDSS_AXI_CLK>, 918 <&mmcc MDSS_MDP_CLK>, 919 <&mmcc MDSS_VSYNC_CLK>; 920 clock-names = "iface", 921 "bus", 922 "core", 923 "vsync"; 924 925 ports { 926 #address-cells = <1>; 927 #size-cells = <0>; 928 929 port@0 { 930 reg = <0>; 931 mdss_mdp_intf1_out: endpoint { 932 remote-endpoint = <&mdss_dsi0_in>; 933 }; 934 }; 935 }; 936 }; 937 938 mdss_dsi0: dsi@fd922800 { 939 compatible = "qcom,msm8226-dsi-ctrl", 940 "qcom,mdss-dsi-ctrl"; 941 reg = <0xfd922800 0x1f8>; 942 reg-names = "dsi_ctrl"; 943 944 interrupt-parent = <&mdss>; 945 interrupts = <4>; 946 947 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 948 <&mmcc PCLK0_CLK_SRC>; 949 assigned-clock-parents = <&mdss_dsi0_phy 0>, 950 <&mdss_dsi0_phy 1>; 951 952 clocks = <&mmcc MDSS_MDP_CLK>, 953 <&mmcc MDSS_AHB_CLK>, 954 <&mmcc MDSS_AXI_CLK>, 955 <&mmcc MDSS_BYTE0_CLK>, 956 <&mmcc MDSS_PCLK0_CLK>, 957 <&mmcc MDSS_ESC0_CLK>, 958 <&mmcc MMSS_MISC_AHB_CLK>; 959 clock-names = "mdp_core", 960 "iface", 961 "bus", 962 "byte", 963 "pixel", 964 "core", 965 "core_mmss"; 966 967 phys = <&mdss_dsi0_phy>; 968 969 #address-cells = <1>; 970 #size-cells = <0>; 971 972 ports { 973 #address-cells = <1>; 974 #size-cells = <0>; 975 976 port@0 { 977 reg = <0>; 978 mdss_dsi0_in: endpoint { 979 remote-endpoint = <&mdss_mdp_intf1_out>; 980 }; 981 }; 982 983 port@1 { 984 reg = <1>; 985 mdss_dsi0_out: endpoint { 986 }; 987 }; 988 }; 989 }; 990 991 mdss_dsi0_phy: phy@fd922a00 { 992 compatible = "qcom,dsi-phy-28nm-8226"; 993 reg = <0xfd922a00 0xd4>, 994 <0xfd922b00 0x280>, 995 <0xfd922d80 0x30>; 996 reg-names = "dsi_pll", 997 "dsi_phy", 998 "dsi_phy_regulator"; 999 1000 #clock-cells = <1>; 1001 #phy-cells = <0>; 1002 1003 clocks = <&mmcc MDSS_AHB_CLK>, 1004 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1005 clock-names = "iface", 1006 "ref"; 1007 }; 1008 }; 1009 }; 1010 1011 thermal-zones { 1012 cpu0-thermal { 1013 polling-delay-passive = <250>; 1014 polling-delay = <1000>; 1015 1016 thermal-sensors = <&tsens 5>; 1017 1018 trips { 1019 cpu_alert0: trip0 { 1020 temperature = <75000>; 1021 hysteresis = <2000>; 1022 type = "passive"; 1023 }; 1024 1025 cpu_crit0: trip1 { 1026 temperature = <110000>; 1027 hysteresis = <2000>; 1028 type = "critical"; 1029 }; 1030 }; 1031 }; 1032 1033 cpu1-thermal { 1034 polling-delay-passive = <250>; 1035 polling-delay = <1000>; 1036 1037 thermal-sensors = <&tsens 2>; 1038 1039 trips { 1040 cpu_alert1: trip0 { 1041 temperature = <75000>; 1042 hysteresis = <2000>; 1043 type = "passive"; 1044 }; 1045 1046 cpu_crit1: trip1 { 1047 temperature = <110000>; 1048 hysteresis = <2000>; 1049 type = "critical"; 1050 }; 1051 }; 1052 }; 1053 }; 1054 1055 timer { 1056 compatible = "arm,armv7-timer"; 1057 interrupts = <GIC_PPI 2 1058 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1059 <GIC_PPI 3 1060 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1061 <GIC_PPI 4 1062 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1063 <GIC_PPI 1 1064 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 1065 }; 1066}; 1067