1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-msm8974.h> 10#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/reset/qcom,gcc-msm8974.h> 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 interrupt-parent = <&intc>; 20 21 chosen { }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0x0 0x0>; 26 }; 27 28 clocks { 29 xo_board: xo_board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <19200000>; 33 }; 34 35 sleep_clk: sleep_clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32768>; 39 }; 40 }; 41 42 firmware { 43 scm { 44 compatible = "qcom,scm-msm8226", "qcom,scm"; 45 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 46 clock-names = "core", "bus", "iface"; 47 }; 48 }; 49 50 pmu { 51 compatible = "arm,cortex-a7-pmu"; 52 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 53 IRQ_TYPE_LEVEL_HIGH)>; 54 }; 55 56 rpm: remoteproc { 57 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; 58 59 smd-edge { 60 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 61 qcom,ipc = <&apcs 8 0>; 62 qcom,smd-edge = <15>; 63 64 rpm_requests: rpm-requests { 65 compatible = "qcom,rpm-msm8226"; 66 qcom,smd-channels = "rpm_requests"; 67 68 rpmcc: clock-controller { 69 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; 70 #clock-cells = <1>; 71 clocks = <&xo_board>; 72 clock-names = "xo"; 73 }; 74 75 rpmpd: power-controller { 76 compatible = "qcom,msm8226-rpmpd"; 77 #power-domain-cells = <1>; 78 operating-points-v2 = <&rpmpd_opp_table>; 79 80 rpmpd_opp_table: opp-table { 81 compatible = "operating-points-v2"; 82 83 rpmpd_opp_ret: opp1 { 84 opp-level = <1>; 85 }; 86 rpmpd_opp_svs_krait: opp2 { 87 opp-level = <2>; 88 }; 89 rpmpd_opp_svs_soc: opp3 { 90 opp-level = <3>; 91 }; 92 rpmpd_opp_nom: opp4 { 93 opp-level = <4>; 94 }; 95 rpmpd_opp_turbo: opp5 { 96 opp-level = <5>; 97 }; 98 rpmpd_opp_super_turbo: opp6 { 99 opp-level = <6>; 100 }; 101 }; 102 }; 103 }; 104 }; 105 }; 106 107 reserved-memory { 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 smem_region: smem@3000000 { 113 reg = <0x3000000 0x100000>; 114 no-map; 115 }; 116 117 adsp_region: adsp@dc00000 { 118 reg = <0x0dc00000 0x1900000>; 119 no-map; 120 }; 121 }; 122 123 smem { 124 compatible = "qcom,smem"; 125 126 memory-region = <&smem_region>; 127 qcom,rpm-msg-ram = <&rpm_msg_ram>; 128 129 hwlocks = <&tcsr_mutex 3>; 130 }; 131 132 smp2p-adsp { 133 compatible = "qcom,smp2p"; 134 qcom,smem = <443>, <429>; 135 136 interrupt-parent = <&intc>; 137 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 138 139 qcom,ipc = <&apcs 8 10>; 140 141 qcom,local-pid = <0>; 142 qcom,remote-pid = <2>; 143 144 adsp_smp2p_out: master-kernel { 145 qcom,entry-name = "master-kernel"; 146 #qcom,smem-state-cells = <1>; 147 }; 148 149 adsp_smp2p_in: slave-kernel { 150 qcom,entry-name = "slave-kernel"; 151 152 interrupt-controller; 153 #interrupt-cells = <2>; 154 }; 155 }; 156 157 soc: soc { 158 compatible = "simple-bus"; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 ranges; 162 163 intc: interrupt-controller@f9000000 { 164 compatible = "qcom,msm-qgic2"; 165 reg = <0xf9000000 0x1000>, 166 <0xf9002000 0x1000>; 167 interrupt-controller; 168 #interrupt-cells = <3>; 169 }; 170 171 apcs: syscon@f9011000 { 172 compatible = "syscon"; 173 reg = <0xf9011000 0x1000>; 174 }; 175 176 sdhc_1: mmc@f9824900 { 177 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 178 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 179 reg-names = "hc", "core"; 180 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 182 interrupt-names = "hc_irq", "pwr_irq"; 183 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 184 <&gcc GCC_SDCC1_APPS_CLK>, 185 <&rpmcc RPM_SMD_XO_CLK_SRC>; 186 clock-names = "iface", "core", "xo"; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&sdhc1_default_state>; 189 status = "disabled"; 190 }; 191 192 sdhc_2: mmc@f98a4900 { 193 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 194 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 195 reg-names = "hc", "core"; 196 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "hc_irq", "pwr_irq"; 199 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 200 <&gcc GCC_SDCC2_APPS_CLK>, 201 <&rpmcc RPM_SMD_XO_CLK_SRC>; 202 clock-names = "iface", "core", "xo"; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&sdhc2_default_state>; 205 status = "disabled"; 206 }; 207 208 sdhc_3: mmc@f9864900 { 209 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 210 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 211 reg-names = "hc", "core"; 212 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "hc_irq", "pwr_irq"; 215 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 216 <&gcc GCC_SDCC3_APPS_CLK>, 217 <&rpmcc RPM_SMD_XO_CLK_SRC>; 218 clock-names = "iface", "core", "xo"; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&sdhc3_default_state>; 221 status = "disabled"; 222 }; 223 224 blsp1_uart1: serial@f991d000 { 225 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 226 reg = <0xf991d000 0x1000>; 227 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 229 clock-names = "core", "iface"; 230 status = "disabled"; 231 }; 232 233 blsp1_uart3: serial@f991f000 { 234 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 235 reg = <0xf991f000 0x1000>; 236 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 238 clock-names = "core", "iface"; 239 status = "disabled"; 240 }; 241 242 blsp1_uart4: serial@f9920000 { 243 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 244 reg = <0xf9920000 0x1000>; 245 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 247 clock-names = "core", "iface"; 248 status = "disabled"; 249 }; 250 251 blsp1_i2c1: i2c@f9923000 { 252 status = "disabled"; 253 compatible = "qcom,i2c-qup-v2.1.1"; 254 reg = <0xf9923000 0x1000>; 255 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 257 clock-names = "core", "iface"; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&blsp1_i2c1_pins>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 }; 263 264 blsp1_i2c2: i2c@f9924000 { 265 status = "disabled"; 266 compatible = "qcom,i2c-qup-v2.1.1"; 267 reg = <0xf9924000 0x1000>; 268 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 270 clock-names = "core", "iface"; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&blsp1_i2c2_pins>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 blsp1_i2c3: i2c@f9925000 { 278 status = "disabled"; 279 compatible = "qcom,i2c-qup-v2.1.1"; 280 reg = <0xf9925000 0x1000>; 281 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 283 clock-names = "core", "iface"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&blsp1_i2c3_pins>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 }; 289 290 blsp1_i2c4: i2c@f9926000 { 291 status = "disabled"; 292 compatible = "qcom,i2c-qup-v2.1.1"; 293 reg = <0xf9926000 0x1000>; 294 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 296 clock-names = "core", "iface"; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&blsp1_i2c4_pins>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 }; 302 303 blsp1_i2c5: i2c@f9927000 { 304 status = "disabled"; 305 compatible = "qcom,i2c-qup-v2.1.1"; 306 reg = <0xf9927000 0x1000>; 307 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 309 clock-names = "core", "iface"; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&blsp1_i2c5_pins>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 316 cci: cci@fda0c000 { 317 compatible = "qcom,msm8226-cci"; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 reg = <0xfda0c000 0x1000>; 321 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 322 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 323 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 324 <&mmcc CAMSS_CCI_CCI_CLK>; 325 clock-names = "camss_top_ahb", 326 "cci_ahb", 327 "cci"; 328 329 pinctrl-names = "default", "sleep"; 330 pinctrl-0 = <&cci_default>; 331 pinctrl-1 = <&cci_sleep>; 332 333 status = "disabled"; 334 335 cci_i2c0: i2c-bus@0 { 336 reg = <0>; 337 clock-frequency = <400000>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 }; 341 }; 342 343 usb: usb@f9a55000 { 344 compatible = "qcom,ci-hdrc"; 345 reg = <0xf9a55000 0x200>, 346 <0xf9a55200 0x200>; 347 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 349 <&gcc GCC_USB_HS_SYSTEM_CLK>; 350 clock-names = "iface", "core"; 351 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 352 assigned-clock-rates = <75000000>; 353 resets = <&gcc GCC_USB_HS_BCR>; 354 reset-names = "core"; 355 phy_type = "ulpi"; 356 dr_mode = "otg"; 357 hnp-disable; 358 srp-disable; 359 adp-disable; 360 ahb-burst-config = <0>; 361 phy-names = "usb-phy"; 362 phys = <&usb_hs_phy>; 363 status = "disabled"; 364 #reset-cells = <1>; 365 366 ulpi { 367 usb_hs_phy: phy { 368 compatible = "qcom,usb-hs-phy-msm8226", 369 "qcom,usb-hs-phy"; 370 #phy-cells = <0>; 371 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 372 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 373 clock-names = "ref", "sleep"; 374 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 375 reset-names = "phy", "por"; 376 qcom,init-seq = /bits/ 8 <0x0 0x44 377 0x1 0x68 0x2 0x24 0x3 0x13>; 378 }; 379 }; 380 }; 381 382 gcc: clock-controller@fc400000 { 383 compatible = "qcom,gcc-msm8226"; 384 reg = <0xfc400000 0x4000>; 385 #clock-cells = <1>; 386 #reset-cells = <1>; 387 #power-domain-cells = <1>; 388 389 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 390 <&sleep_clk>; 391 clock-names = "xo", 392 "sleep_clk"; 393 }; 394 395 mmcc: clock-controller@fd8c0000 { 396 compatible = "qcom,mmcc-msm8226"; 397 reg = <0xfd8c0000 0x6000>; 398 #clock-cells = <1>; 399 #reset-cells = <1>; 400 #power-domain-cells = <1>; 401 402 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 403 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 404 <&gcc GPLL0_VOTE>, 405 <&gcc GPLL1_VOTE>, 406 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 407 <0>, 408 <0>; 409 clock-names = "xo", 410 "mmss_gpll0_vote", 411 "gpll0_vote", 412 "gpll1_vote", 413 "gfx3d_clk_src", 414 "dsi0pll", 415 "dsi0pllbyte"; 416 }; 417 418 tlmm: pinctrl@fd510000 { 419 compatible = "qcom,msm8226-pinctrl"; 420 reg = <0xfd510000 0x4000>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 gpio-ranges = <&tlmm 0 0 117>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 427 428 blsp1_i2c1_pins: blsp1-i2c1-state { 429 pins = "gpio2", "gpio3"; 430 function = "blsp_i2c1"; 431 drive-strength = <2>; 432 bias-disable; 433 }; 434 435 blsp1_i2c2_pins: blsp1-i2c2-state { 436 pins = "gpio6", "gpio7"; 437 function = "blsp_i2c2"; 438 drive-strength = <2>; 439 bias-disable; 440 }; 441 442 blsp1_i2c3_pins: blsp1-i2c3-state { 443 pins = "gpio10", "gpio11"; 444 function = "blsp_i2c3"; 445 drive-strength = <2>; 446 bias-disable; 447 }; 448 449 blsp1_i2c4_pins: blsp1-i2c4-state { 450 pins = "gpio14", "gpio15"; 451 function = "blsp_i2c4"; 452 drive-strength = <2>; 453 bias-disable; 454 }; 455 456 blsp1_i2c5_pins: blsp1-i2c5-state { 457 pins = "gpio18", "gpio19"; 458 function = "blsp_i2c5"; 459 drive-strength = <2>; 460 bias-disable; 461 }; 462 463 cci_default: cci-default-state { 464 pins = "gpio29", "gpio30"; 465 function = "cci_i2c0"; 466 467 drive-strength = <2>; 468 bias-disable; 469 }; 470 471 cci_sleep: cci-sleep-state { 472 pins = "gpio29", "gpio30"; 473 function = "gpio"; 474 475 drive-strength = <2>; 476 bias-disable; 477 }; 478 479 sdhc1_default_state: sdhc1-default-state { 480 clk-pins { 481 pins = "sdc1_clk"; 482 drive-strength = <10>; 483 bias-disable; 484 }; 485 486 cmd-data-pins { 487 pins = "sdc1_cmd", "sdc1_data"; 488 drive-strength = <10>; 489 bias-pull-up; 490 }; 491 }; 492 493 sdhc2_default_state: sdhc2-default-state { 494 clk-pins { 495 pins = "sdc2_clk"; 496 drive-strength = <10>; 497 bias-disable; 498 }; 499 500 cmd-data-pins { 501 pins = "sdc2_cmd", "sdc2_data"; 502 drive-strength = <10>; 503 bias-pull-up; 504 }; 505 }; 506 507 sdhc3_default_state: sdhc3-default-state { 508 clk-pins { 509 pins = "gpio44"; 510 function = "sdc3"; 511 drive-strength = <8>; 512 bias-disable; 513 }; 514 515 cmd-pins { 516 pins = "gpio43"; 517 function = "sdc3"; 518 drive-strength = <8>; 519 bias-pull-up; 520 }; 521 522 data-pins { 523 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 524 function = "sdc3"; 525 drive-strength = <8>; 526 bias-pull-up; 527 }; 528 }; 529 }; 530 531 tsens: thermal-sensor@fc4a9000 { 532 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; 533 reg = <0xfc4a9000 0x1000>, /* TM */ 534 <0xfc4a8000 0x1000>; /* SROT */ 535 nvmem-cells = <&tsens_mode>, 536 <&tsens_base1>, <&tsens_base2>, 537 <&tsens_s0_p1>, <&tsens_s0_p2>, 538 <&tsens_s1_p1>, <&tsens_s1_p2>, 539 <&tsens_s2_p1>, <&tsens_s2_p2>, 540 <&tsens_s3_p1>, <&tsens_s3_p2>, 541 <&tsens_s4_p1>, <&tsens_s4_p2>, 542 <&tsens_s5_p1>, <&tsens_s5_p2>, 543 <&tsens_s6_p1>, <&tsens_s6_p2>; 544 nvmem-cell-names = "mode", 545 "base1", "base2", 546 "s0_p1", "s0_p2", 547 "s1_p1", "s1_p2", 548 "s2_p1", "s2_p2", 549 "s3_p1", "s3_p2", 550 "s4_p1", "s4_p2", 551 "s5_p1", "s5_p2", 552 "s6_p1", "s6_p2"; 553 #qcom,sensors = <6>; 554 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 555 interrupt-names = "uplow"; 556 #thermal-sensor-cells = <1>; 557 }; 558 559 restart@fc4ab000 { 560 compatible = "qcom,pshold"; 561 reg = <0xfc4ab000 0x4>; 562 }; 563 564 qfprom: qfprom@fc4bc000 { 565 compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; 566 reg = <0xfc4bc000 0x1000>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 570 tsens_base1: base1@1c1 { 571 reg = <0x1c1 0x2>; 572 bits = <5 8>; 573 }; 574 575 tsens_s0_p1: s0-p1@1c2 { 576 reg = <0x1c2 0x2>; 577 bits = <5 6>; 578 }; 579 580 tsens_s1_p1: s1-p1@1c4 { 581 reg = <0x1c4 0x1>; 582 bits = <0 6>; 583 }; 584 585 tsens_s2_p1: s2-p1@1c4 { 586 reg = <0x1c4 0x2>; 587 bits = <6 6>; 588 }; 589 590 tsens_s3_p1: s3-p1@1c5 { 591 reg = <0x1c5 0x2>; 592 bits = <4 6>; 593 }; 594 595 tsens_s4_p1: s4-p1@1c6 { 596 reg = <0x1c6 0x1>; 597 bits = <2 6>; 598 }; 599 600 tsens_s5_p1: s5-p1@1c7 { 601 reg = <0x1c7 0x1>; 602 bits = <0 6>; 603 }; 604 605 tsens_s6_p1: s6-p1@1ca { 606 reg = <0x1ca 0x2>; 607 bits = <4 6>; 608 }; 609 610 tsens_base2: base2@1cc { 611 reg = <0x1cc 0x1>; 612 bits = <0 8>; 613 }; 614 615 tsens_s0_p2: s0-p2@1cd { 616 reg = <0x1cd 0x1>; 617 bits = <0 6>; 618 }; 619 620 tsens_s1_p2: s1-p2@1cd { 621 reg = <0x1cd 0x2>; 622 bits = <6 6>; 623 }; 624 625 tsens_s2_p2: s2-p2@1ce { 626 reg = <0x1ce 0x2>; 627 bits = <4 6>; 628 }; 629 630 tsens_s3_p2: s3-p2@1cf { 631 reg = <0x1cf 0x1>; 632 bits = <2 6>; 633 }; 634 635 tsens_s4_p2: s4-p2@446 { 636 reg = <0x446 0x2>; 637 bits = <4 6>; 638 }; 639 640 tsens_s5_p2: s5-p2@447 { 641 reg = <0x447 0x1>; 642 bits = <2 6>; 643 }; 644 645 tsens_s6_p2: s6-p2@44e { 646 reg = <0x44e 0x1>; 647 bits = <1 6>; 648 }; 649 650 tsens_mode: mode@44f { 651 reg = <0x44f 0x1>; 652 bits = <5 3>; 653 }; 654 }; 655 656 spmi_bus: spmi@fc4cf000 { 657 compatible = "qcom,spmi-pmic-arb"; 658 reg-names = "core", "intr", "cnfg"; 659 reg = <0xfc4cf000 0x1000>, 660 <0xfc4cb000 0x1000>, 661 <0xfc4ca000 0x1000>; 662 interrupt-names = "periph_irq"; 663 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 664 qcom,ee = <0>; 665 qcom,channel = <0>; 666 #address-cells = <2>; 667 #size-cells = <0>; 668 interrupt-controller; 669 #interrupt-cells = <4>; 670 }; 671 672 rng@f9bff000 { 673 compatible = "qcom,prng"; 674 reg = <0xf9bff000 0x200>; 675 clocks = <&gcc GCC_PRNG_AHB_CLK>; 676 clock-names = "core"; 677 }; 678 679 timer@f9020000 { 680 compatible = "arm,armv7-timer-mem"; 681 reg = <0xf9020000 0x1000>; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges; 685 686 frame@f9021000 { 687 frame-number = <0>; 688 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 690 reg = <0xf9021000 0x1000>, 691 <0xf9022000 0x1000>; 692 }; 693 694 frame@f9023000 { 695 frame-number = <1>; 696 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 697 reg = <0xf9023000 0x1000>; 698 status = "disabled"; 699 }; 700 701 frame@f9024000 { 702 frame-number = <2>; 703 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 704 reg = <0xf9024000 0x1000>; 705 status = "disabled"; 706 }; 707 708 frame@f9025000 { 709 frame-number = <3>; 710 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 711 reg = <0xf9025000 0x1000>; 712 status = "disabled"; 713 }; 714 715 frame@f9026000 { 716 frame-number = <4>; 717 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 718 reg = <0xf9026000 0x1000>; 719 status = "disabled"; 720 }; 721 722 frame@f9027000 { 723 frame-number = <5>; 724 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 725 reg = <0xf9027000 0x1000>; 726 status = "disabled"; 727 }; 728 729 frame@f9028000 { 730 frame-number = <6>; 731 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 732 reg = <0xf9028000 0x1000>; 733 status = "disabled"; 734 }; 735 }; 736 737 sram@fc190000 { 738 compatible = "qcom,msm8226-rpm-stats"; 739 reg = <0xfc190000 0x10000>; 740 }; 741 742 rpm_msg_ram: sram@fc428000 { 743 compatible = "qcom,rpm-msg-ram"; 744 reg = <0xfc428000 0x4000>; 745 }; 746 747 tcsr_mutex: hwlock@fd484000 { 748 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; 749 reg = <0xfd484000 0x1000>; 750 #hwlock-cells = <1>; 751 }; 752 753 adsp: remoteproc@fe200000 { 754 compatible = "qcom,msm8226-adsp-pil"; 755 reg = <0xfe200000 0x100>; 756 757 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 758 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 759 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 760 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 761 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 762 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 763 764 power-domains = <&rpmpd MSM8226_VDDCX>; 765 power-domain-names = "cx"; 766 767 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 768 clock-names = "xo"; 769 770 memory-region = <&adsp_region>; 771 772 qcom,smem-states = <&adsp_smp2p_out 0>; 773 qcom,smem-state-names = "stop"; 774 775 status = "disabled"; 776 777 smd-edge { 778 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 779 780 qcom,ipc = <&apcs 8 8>; 781 qcom,smd-edge = <1>; 782 783 label = "lpass"; 784 }; 785 }; 786 787 sram@fdd00000 { 788 compatible = "qcom,msm8226-ocmem"; 789 reg = <0xfdd00000 0x2000>, 790 <0xfec00000 0x20000>; 791 reg-names = "ctrl", "mem"; 792 ranges = <0 0xfec00000 0x20000>; 793 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; 794 clock-names = "core"; 795 796 #address-cells = <1>; 797 #size-cells = <1>; 798 799 gmu_sram: gmu-sram@0 { 800 reg = <0x0 0x20000>; 801 }; 802 }; 803 804 sram@fe805000 { 805 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 806 reg = <0xfe805000 0x1000>; 807 808 reboot-mode { 809 compatible = "syscon-reboot-mode"; 810 offset = <0x65c>; 811 812 mode-bootloader = <0x77665500>; 813 mode-normal = <0x77665501>; 814 mode-recovery = <0x77665502>; 815 }; 816 }; 817 818 mdss: display-subsystem@fd900000 { 819 compatible = "qcom,mdss"; 820 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 821 reg-names = "mdss_phys", "vbif_phys"; 822 823 power-domains = <&mmcc MDSS_GDSC>; 824 825 clocks = <&mmcc MDSS_AHB_CLK>, 826 <&mmcc MDSS_AXI_CLK>, 827 <&mmcc MDSS_VSYNC_CLK>; 828 clock-names = "iface", 829 "bus", 830 "vsync"; 831 832 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 833 834 interrupt-controller; 835 #interrupt-cells = <1>; 836 837 #address-cells = <1>; 838 #size-cells = <1>; 839 ranges; 840 841 status = "disabled"; 842 843 mdss_mdp: display-controller@fd900000 { 844 compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; 845 reg = <0xfd900100 0x22000>; 846 reg-names = "mdp_phys"; 847 848 interrupt-parent = <&mdss>; 849 interrupts = <0>; 850 851 clocks = <&mmcc MDSS_AHB_CLK>, 852 <&mmcc MDSS_AXI_CLK>, 853 <&mmcc MDSS_MDP_CLK>, 854 <&mmcc MDSS_VSYNC_CLK>; 855 clock-names = "iface", 856 "bus", 857 "core", 858 "vsync"; 859 860 ports { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 864 port@0 { 865 reg = <0>; 866 mdss_mdp_intf1_out: endpoint { 867 remote-endpoint = <&mdss_dsi0_in>; 868 }; 869 }; 870 }; 871 }; 872 873 mdss_dsi0: dsi@fd922800 { 874 compatible = "qcom,msm8226-dsi-ctrl", 875 "qcom,mdss-dsi-ctrl"; 876 reg = <0xfd922800 0x1f8>; 877 reg-names = "dsi_ctrl"; 878 879 interrupt-parent = <&mdss>; 880 interrupts = <4>; 881 882 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 883 <&mmcc PCLK0_CLK_SRC>; 884 assigned-clock-parents = <&mdss_dsi0_phy 0>, 885 <&mdss_dsi0_phy 1>; 886 887 clocks = <&mmcc MDSS_MDP_CLK>, 888 <&mmcc MDSS_AHB_CLK>, 889 <&mmcc MDSS_AXI_CLK>, 890 <&mmcc MDSS_BYTE0_CLK>, 891 <&mmcc MDSS_PCLK0_CLK>, 892 <&mmcc MDSS_ESC0_CLK>, 893 <&mmcc MMSS_MISC_AHB_CLK>; 894 clock-names = "mdp_core", 895 "iface", 896 "bus", 897 "byte", 898 "pixel", 899 "core", 900 "core_mmss"; 901 902 phys = <&mdss_dsi0_phy>; 903 904 #address-cells = <1>; 905 #size-cells = <0>; 906 907 ports { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 port@0 { 912 reg = <0>; 913 mdss_dsi0_in: endpoint { 914 remote-endpoint = <&mdss_mdp_intf1_out>; 915 }; 916 }; 917 918 port@1 { 919 reg = <1>; 920 mdss_dsi0_out: endpoint { 921 }; 922 }; 923 }; 924 }; 925 926 mdss_dsi0_phy: phy@fd922a00 { 927 compatible = "qcom,dsi-phy-28nm-8226"; 928 reg = <0xfd922a00 0xd4>, 929 <0xfd922b00 0x280>, 930 <0xfd922d80 0x30>; 931 reg-names = "dsi_pll", 932 "dsi_phy", 933 "dsi_phy_regulator"; 934 935 #clock-cells = <1>; 936 #phy-cells = <0>; 937 938 clocks = <&mmcc MDSS_AHB_CLK>, 939 <&rpmcc RPM_SMD_XO_CLK_SRC>; 940 clock-names = "iface", 941 "ref"; 942 }; 943 }; 944 }; 945 946 thermal-zones { 947 cpu0-thermal { 948 polling-delay-passive = <250>; 949 polling-delay = <1000>; 950 951 thermal-sensors = <&tsens 5>; 952 953 trips { 954 cpu_alert0: trip0 { 955 temperature = <75000>; 956 hysteresis = <2000>; 957 type = "passive"; 958 }; 959 960 cpu_crit0: trip1 { 961 temperature = <110000>; 962 hysteresis = <2000>; 963 type = "critical"; 964 }; 965 }; 966 }; 967 968 cpu1-thermal { 969 polling-delay-passive = <250>; 970 polling-delay = <1000>; 971 972 thermal-sensors = <&tsens 2>; 973 974 trips { 975 cpu_alert1: trip0 { 976 temperature = <75000>; 977 hysteresis = <2000>; 978 type = "passive"; 979 }; 980 981 cpu_crit1: trip1 { 982 temperature = <110000>; 983 hysteresis = <2000>; 984 type = "critical"; 985 }; 986 }; 987 }; 988 }; 989 990 timer { 991 compatible = "arm,armv7-timer"; 992 interrupts = <GIC_PPI 2 993 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 994 <GIC_PPI 3 995 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 996 <GIC_PPI 4 997 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 998 <GIC_PPI 1 999 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 1000 }; 1001}; 1002