1 /* 2 * Common defines for v7m cpus 3 */ 4 #define V7M_SCS_ICTR IOMEM(0xe000e004) 5 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f 6 7 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) 8 9 #define V7M_SCB_CPUID 0x00 10 11 #define V7M_SCB_ICSR 0x04 12 #define V7M_SCB_ICSR_PENDSVSET (1 << 28) 13 #define V7M_SCB_ICSR_PENDSVCLR (1 << 27) 14 #define V7M_SCB_ICSR_RETTOBASE (1 << 11) 15 16 #define V7M_SCB_VTOR 0x08 17 18 #define V7M_SCB_SCR 0x10 19 #define V7M_SCB_SCR_SLEEPDEEP (1 << 2) 20 21 #define V7M_SCB_CCR 0x14 22 #define V7M_SCB_CCR_STKALIGN (1 << 9) 23 24 #define V7M_SCB_SHPR2 0x1c 25 #define V7M_SCB_SHPR3 0x20 26 27 #define V7M_SCB_SHCSR 0x24 28 #define V7M_SCB_SHCSR_USGFAULTENA (1 << 18) 29 #define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17) 30 #define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) 31 32 #define V7M_xPSR_FRAMEPTRALIGN 0x00000200 33 #define V7M_xPSR_EXCEPTIONNO 0x000001ff 34 35 /* 36 * When branching to an address that has bits [31:28] == 0xf an exception return 37 * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP 38 * extension Bit [4] defines if the exception frame has space allocated for FP 39 * state information, SBOP otherwise. Bit [3] defines the mode that is returned 40 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used 41 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01. 42 */ 43 #define EXC_RET_STACK_MASK 0x00000004 44 #define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd 45