1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 */ 5 #include <linux/irqchip.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 8 #include <linux/of_platform.h> 9 #include <linux/phy.h> 10 #include <linux/regmap.h> 11 12 #include <asm/mach/arch.h> 13 #include <asm/mach/map.h> 14 15 #include "common.h" 16 17 static int ar8031_phy_fixup(struct phy_device *dev) 18 { 19 u16 val; 20 21 /* Set RGMII IO voltage to 1.8V */ 22 phy_write(dev, 0x1d, 0x1f); 23 phy_write(dev, 0x1e, 0x8); 24 25 /* disable phy AR8031 SmartEEE function. */ 26 phy_write(dev, 0xd, 0x3); 27 phy_write(dev, 0xe, 0x805d); 28 phy_write(dev, 0xd, 0x4003); 29 val = phy_read(dev, 0xe); 30 val &= ~(0x1 << 8); 31 phy_write(dev, 0xe, val); 32 33 /* introduce tx clock delay */ 34 phy_write(dev, 0x1d, 0x5); 35 val = phy_read(dev, 0x1e); 36 val |= 0x0100; 37 phy_write(dev, 0x1e, val); 38 39 return 0; 40 } 41 42 static int bcm54220_phy_fixup(struct phy_device *dev) 43 { 44 /* enable RXC skew select RGMII copper mode */ 45 phy_write(dev, 0x1e, 0x21); 46 phy_write(dev, 0x1f, 0x7ea8); 47 phy_write(dev, 0x1e, 0x2f); 48 phy_write(dev, 0x1f, 0x71b7); 49 50 return 0; 51 } 52 53 #define PHY_ID_AR8031 0x004dd074 54 #define PHY_ID_BCM54220 0x600d8589 55 56 static void __init imx7d_enet_phy_init(void) 57 { 58 if (IS_BUILTIN(CONFIG_PHYLIB)) { 59 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, 60 ar8031_phy_fixup); 61 phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff, 62 bcm54220_phy_fixup); 63 } 64 } 65 66 static void __init imx7d_enet_clk_sel(void) 67 { 68 struct regmap *gpr; 69 70 gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); 71 if (!IS_ERR(gpr)) { 72 regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); 73 regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); 74 } else { 75 pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); 76 } 77 } 78 79 static inline void imx7d_enet_init(void) 80 { 81 imx7d_enet_phy_init(); 82 imx7d_enet_clk_sel(); 83 } 84 85 static void __init imx7d_init_machine(void) 86 { 87 struct device *parent; 88 89 parent = imx_soc_device_init(); 90 if (parent == NULL) 91 pr_warn("failed to initialize soc device\n"); 92 93 imx_anatop_init(); 94 imx7d_enet_init(); 95 } 96 97 static void __init imx7d_init_irq(void) 98 { 99 imx_init_revision_from_anatop(); 100 imx_src_init(); 101 irqchip_init(); 102 } 103 104 static const char *const imx7d_dt_compat[] __initconst = { 105 "fsl,imx7d", 106 "fsl,imx7s", 107 NULL, 108 }; 109 110 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") 111 .init_irq = imx7d_init_irq, 112 .init_machine = imx7d_init_machine, 113 .dt_compat = imx7d_dt_compat, 114 MACHINE_END 115