1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DPLL + CORE_CLK composite clock functions 4 * 5 * Copyright (C) 2005-2008 Texas Instruments, Inc. 6 * Copyright (C) 2004-2010 Nokia Corporation 7 * 8 * Contacts: 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Paul Walmsley 11 * 12 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, 13 * Gordon McNutt and RidgeRun, Inc. 14 * 15 * XXX The DPLL and CORE clocks should be split into two separate clock 16 * types. 17 */ 18 #undef DEBUG 19 20 #include <linux/kernel.h> 21 #include <linux/errno.h> 22 #include <linux/clk.h> 23 #include <linux/io.h> 24 25 #include "clock.h" 26 #include "clock2xxx.h" 27 #include "opp2xxx.h" 28 #include "cm2xxx.h" 29 #include "cm-regbits-24xx.h" 30 #include "sdrc.h" 31 #include "sram.h" 32 33 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ 34 35 /* 36 * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx 37 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set 38 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). 39 */ 40 static struct clk_hw_omap *dpll_core_ck; 41 42 /** 43 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate 44 * 45 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate 46 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz 47 * (the latter is unusual). This currently should be called with 48 * struct clk *dpll_ck, which is a composite clock of dpll_ck and 49 * core_ck. 50 */ 51 unsigned long omap2xxx_clk_get_core_rate(void) 52 { 53 long long core_clk; 54 u32 v; 55 56 WARN_ON(!dpll_core_ck); 57 58 core_clk = omap2_get_dpll_rate(dpll_core_ck); 59 60 v = omap2xxx_cm_get_core_clk_src(); 61 62 if (v == CORE_CLK_SRC_32K) 63 core_clk = 32768; 64 else 65 core_clk *= v; 66 67 return core_clk; 68 } 69 70 /* 71 * Uses the current prcm set to tell if a rate is valid. 72 * You can go slower, but not faster within a given rate set. 73 */ 74 static long omap2_dpllcore_round_rate(unsigned long target_rate) 75 { 76 u32 high, low, core_clk_src; 77 78 core_clk_src = omap2xxx_cm_get_core_clk_src(); 79 80 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ 81 high = curr_prcm_set->dpll_speed * 2; 82 low = curr_prcm_set->dpll_speed; 83 } else { /* DPLL clockout x 2 */ 84 high = curr_prcm_set->dpll_speed; 85 low = curr_prcm_set->dpll_speed / 2; 86 } 87 88 #ifdef DOWN_VARIABLE_DPLL 89 if (target_rate > high) 90 return high; 91 else 92 return target_rate; 93 #else 94 if (target_rate > low) 95 return high; 96 else 97 return low; 98 #endif 99 100 } 101 102 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, 103 unsigned long parent_rate) 104 { 105 return omap2xxx_clk_get_core_rate(); 106 } 107 108 int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, 109 unsigned long parent_rate) 110 { 111 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 112 u32 cur_rate, low, mult, div, valid_rate, done_rate; 113 u32 bypass = 0; 114 struct prcm_config tmpset; 115 const struct dpll_data *dd; 116 117 cur_rate = omap2xxx_clk_get_core_rate(); 118 mult = omap2xxx_cm_get_core_clk_src(); 119 120 if ((rate == (cur_rate / 2)) && (mult == 2)) { 121 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); 122 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { 123 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); 124 } else if (rate != cur_rate) { 125 valid_rate = omap2_dpllcore_round_rate(rate); 126 if (valid_rate != rate) 127 return -EINVAL; 128 129 if (mult == 1) 130 low = curr_prcm_set->dpll_speed; 131 else 132 low = curr_prcm_set->dpll_speed / 2; 133 134 dd = clk->dpll_data; 135 if (!dd) 136 return -EINVAL; 137 138 tmpset.cm_clksel1_pll = 139 omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg); 140 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 141 dd->div1_mask); 142 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 143 tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config(); 144 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; 145 if (rate > low) { 146 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; 147 mult = ((rate / 2) / 1000000); 148 done_rate = CORE_CLK_SRC_DPLL_X2; 149 } else { 150 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; 151 mult = (rate / 1000000); 152 done_rate = CORE_CLK_SRC_DPLL; 153 } 154 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); 155 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); 156 157 /* Worst case */ 158 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; 159 160 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ 161 bypass = 1; 162 163 /* For omap2xxx_sdrc_init_params() */ 164 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); 165 166 /* Force dll lock mode */ 167 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, 168 bypass); 169 170 /* Errata: ret dll entry state */ 171 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); 172 omap2xxx_sdrc_reprogram(done_rate, 0); 173 } 174 175 return 0; 176 } 177 178 /** 179 * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck 180 * @clk: struct clk *dpll_ck 181 * 182 * Store a local copy of @clk in dpll_core_ck so other code can query 183 * the core rate without having to clk_get(), which can sleep. Must 184 * only be called once. No return value. XXX If the clock 185 * registration process is ever changed such that dpll_ck is no longer 186 * statically defined, this code may need to change to increment some 187 * kind of use count on dpll_ck. 188 */ 189 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw) 190 { 191 WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); 192 dpll_core_ck = to_clk_hw_omap(hw); 193 } 194