1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI81XX Clock Domain data. 4 * 5 * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/ 6 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ 7 */ 8 9 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H 10 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H 11 12 #include <linux/kernel.h> 13 #include <linux/io.h> 14 15 #include "clockdomain.h" 16 #include "cm81xx.h" 17 18 /* 19 * Note that 814x seems to have HWSUP_SWSUP for many clockdomains 20 * while 816x does not. According to the TRM, 816x only has HWSUP 21 * for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h 22 * seems to have the related ifdef the wrong way around claiming 23 * 816x supports HWSUP while 814x does not. For now, we only set 24 * HWSUP for ALWON_L3_FAST as that seems to be supported for both 25 * dm814x and dm816x. 26 */ 27 28 /* Common for 81xx */ 29 30 static struct clockdomain alwon_l3_slow_81xx_clkdm = { 31 .name = "alwon_l3s_clkdm", 32 .pwrdm = { .name = "alwon_pwrdm" }, 33 .cm_inst = TI81XX_CM_ALWON_MOD, 34 .clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM, 35 .flags = CLKDM_CAN_SWSUP, 36 }; 37 38 static struct clockdomain alwon_l3_med_81xx_clkdm = { 39 .name = "alwon_l3_med_clkdm", 40 .pwrdm = { .name = "alwon_pwrdm" }, 41 .cm_inst = TI81XX_CM_ALWON_MOD, 42 .clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM, 43 .flags = CLKDM_CAN_SWSUP, 44 }; 45 46 static struct clockdomain alwon_l3_fast_81xx_clkdm = { 47 .name = "alwon_l3_fast_clkdm", 48 .pwrdm = { .name = "alwon_pwrdm" }, 49 .cm_inst = TI81XX_CM_ALWON_MOD, 50 .clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM, 51 .flags = CLKDM_CAN_HWSUP_SWSUP, 52 }; 53 54 static struct clockdomain alwon_ethernet_81xx_clkdm = { 55 .name = "alwon_ethernet_clkdm", 56 .pwrdm = { .name = "alwon_pwrdm" }, 57 .cm_inst = TI81XX_CM_ALWON_MOD, 58 .clkdm_offs = TI81XX_CM_ETHERNET_CLKDM, 59 .flags = CLKDM_CAN_SWSUP, 60 }; 61 62 static struct clockdomain mmu_81xx_clkdm = { 63 .name = "mmu_clkdm", 64 .pwrdm = { .name = "alwon_pwrdm" }, 65 .cm_inst = TI81XX_CM_ALWON_MOD, 66 .clkdm_offs = TI81XX_CM_MMU_CLKDM, 67 .flags = CLKDM_CAN_SWSUP, 68 }; 69 70 static struct clockdomain mmu_cfg_81xx_clkdm = { 71 .name = "mmu_cfg_clkdm", 72 .pwrdm = { .name = "alwon_pwrdm" }, 73 .cm_inst = TI81XX_CM_ALWON_MOD, 74 .clkdm_offs = TI81XX_CM_MMUCFG_CLKDM, 75 .flags = CLKDM_CAN_SWSUP, 76 }; 77 78 static struct clockdomain default_l3_slow_81xx_clkdm = { 79 .name = "default_l3_slow_clkdm", 80 .pwrdm = { .name = "default_pwrdm" }, 81 .cm_inst = TI81XX_CM_DEFAULT_MOD, 82 .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM, 83 .flags = CLKDM_CAN_SWSUP, 84 }; 85 86 static struct clockdomain default_sata_81xx_clkdm = { 87 .name = "default_clkdm", 88 .pwrdm = { .name = "default_pwrdm" }, 89 .cm_inst = TI81XX_CM_DEFAULT_MOD, 90 .clkdm_offs = TI816X_CM_DEFAULT_SATA_CLKDM, 91 .flags = CLKDM_CAN_SWSUP, 92 }; 93 94 /* 816x only */ 95 96 static struct clockdomain alwon_mpu_816x_clkdm = { 97 .name = "alwon_mpu_clkdm", 98 .pwrdm = { .name = "alwon_pwrdm" }, 99 .cm_inst = TI81XX_CM_ALWON_MOD, 100 .clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM, 101 .flags = CLKDM_CAN_SWSUP, 102 }; 103 104 static struct clockdomain active_gem_816x_clkdm = { 105 .name = "active_gem_clkdm", 106 .pwrdm = { .name = "active_pwrdm" }, 107 .cm_inst = TI81XX_CM_ACTIVE_MOD, 108 .clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM, 109 .flags = CLKDM_CAN_SWSUP, 110 }; 111 112 static struct clockdomain ivahd0_816x_clkdm = { 113 .name = "ivahd0_clkdm", 114 .pwrdm = { .name = "ivahd0_pwrdm" }, 115 .cm_inst = TI816X_CM_IVAHD0_MOD, 116 .clkdm_offs = TI816X_CM_IVAHD0_CLKDM, 117 .flags = CLKDM_CAN_SWSUP, 118 }; 119 120 static struct clockdomain ivahd1_816x_clkdm = { 121 .name = "ivahd1_clkdm", 122 .pwrdm = { .name = "ivahd1_pwrdm" }, 123 .cm_inst = TI816X_CM_IVAHD1_MOD, 124 .clkdm_offs = TI816X_CM_IVAHD1_CLKDM, 125 .flags = CLKDM_CAN_SWSUP, 126 }; 127 128 static struct clockdomain ivahd2_816x_clkdm = { 129 .name = "ivahd2_clkdm", 130 .pwrdm = { .name = "ivahd2_pwrdm" }, 131 .cm_inst = TI816X_CM_IVAHD2_MOD, 132 .clkdm_offs = TI816X_CM_IVAHD2_CLKDM, 133 .flags = CLKDM_CAN_SWSUP, 134 }; 135 136 static struct clockdomain sgx_816x_clkdm = { 137 .name = "sgx_clkdm", 138 .pwrdm = { .name = "sgx_pwrdm" }, 139 .cm_inst = TI81XX_CM_SGX_MOD, 140 .clkdm_offs = TI816X_CM_SGX_CLKDM, 141 .flags = CLKDM_CAN_SWSUP, 142 }; 143 144 static struct clockdomain default_l3_med_816x_clkdm = { 145 .name = "default_l3_med_clkdm", 146 .pwrdm = { .name = "default_pwrdm" }, 147 .cm_inst = TI81XX_CM_DEFAULT_MOD, 148 .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM, 149 .flags = CLKDM_CAN_SWSUP, 150 }; 151 152 static struct clockdomain default_ducati_816x_clkdm = { 153 .name = "default_ducati_clkdm", 154 .pwrdm = { .name = "default_pwrdm" }, 155 .cm_inst = TI81XX_CM_DEFAULT_MOD, 156 .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM, 157 .flags = CLKDM_CAN_SWSUP, 158 }; 159 160 static struct clockdomain default_pci_816x_clkdm = { 161 .name = "default_pci_clkdm", 162 .pwrdm = { .name = "default_pwrdm" }, 163 .cm_inst = TI81XX_CM_DEFAULT_MOD, 164 .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM, 165 .flags = CLKDM_CAN_SWSUP, 166 }; 167 168 static struct clockdomain *clockdomains_ti814x[] __initdata = { 169 &alwon_l3_slow_81xx_clkdm, 170 &alwon_l3_med_81xx_clkdm, 171 &alwon_l3_fast_81xx_clkdm, 172 &alwon_ethernet_81xx_clkdm, 173 &mmu_81xx_clkdm, 174 &mmu_cfg_81xx_clkdm, 175 &default_l3_slow_81xx_clkdm, 176 &default_sata_81xx_clkdm, 177 NULL, 178 }; 179 180 void __init ti814x_clockdomains_init(void) 181 { 182 clkdm_register_platform_funcs(&am33xx_clkdm_operations); 183 clkdm_register_clkdms(clockdomains_ti814x); 184 clkdm_complete_init(); 185 } 186 187 static struct clockdomain *clockdomains_ti816x[] __initdata = { 188 &alwon_mpu_816x_clkdm, 189 &alwon_l3_slow_81xx_clkdm, 190 &alwon_l3_med_81xx_clkdm, 191 &alwon_l3_fast_81xx_clkdm, 192 &alwon_ethernet_81xx_clkdm, 193 &mmu_81xx_clkdm, 194 &mmu_cfg_81xx_clkdm, 195 &active_gem_816x_clkdm, 196 &ivahd0_816x_clkdm, 197 &ivahd1_816x_clkdm, 198 &ivahd2_816x_clkdm, 199 &sgx_816x_clkdm, 200 &default_l3_med_816x_clkdm, 201 &default_ducati_816x_clkdm, 202 &default_pci_816x_clkdm, 203 &default_l3_slow_81xx_clkdm, 204 &default_sata_81xx_clkdm, 205 NULL, 206 }; 207 208 void __init ti816x_clockdomains_init(void) 209 { 210 clkdm_register_platform_funcs(&am33xx_clkdm_operations); 211 clkdm_register_clkdms(clockdomains_ti816x); 212 clkdm_complete_init(); 213 } 214 #endif 215