1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AM33XX Arch Power Management Routines 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * Dave Gerlach 7 */ 8 9 #include <asm/smp_scu.h> 10 #include <asm/suspend.h> 11 #include <linux/errno.h> 12 #include <linux/platform_data/pm33xx.h> 13 #include <linux/clk.h> 14 #include <linux/platform_data/gpio-omap.h> 15 #include <linux/pinctrl/pinmux.h> 16 #include <linux/wkup_m3_ipc.h> 17 #include <linux/of.h> 18 #include <linux/rtc.h> 19 20 #include "cm33xx.h" 21 #include "common.h" 22 #include "control.h" 23 #include "clockdomain.h" 24 #include "iomap.h" 25 #include "omap_hwmod.h" 26 #include "pm.h" 27 #include "powerdomain.h" 28 #include "prm33xx.h" 29 #include "soc.h" 30 #include "sram.h" 31 #include "omap-secure.h" 32 33 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; 34 static struct clockdomain *gfx_l4ls_clkdm; 35 static void __iomem *scu_base; 36 static struct omap_hwmod *rtc_oh; 37 38 static int am43xx_map_scu(void) 39 { 40 scu_base = ioremap(scu_a9_get_base(), SZ_256); 41 42 if (!scu_base) 43 return -ENOMEM; 44 45 return 0; 46 } 47 48 static int am33xx_check_off_mode_enable(void) 49 { 50 if (enable_off_mode) 51 pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n"); 52 53 /* off mode not supported on am335x so return 0 always */ 54 return 0; 55 } 56 57 static int am43xx_check_off_mode_enable(void) 58 { 59 /* 60 * Check for am437x-gp-evm which has the right Hardware design to 61 * support this mode reliably. 62 */ 63 if (of_machine_is_compatible("ti,am437x-gp-evm") && enable_off_mode) 64 return enable_off_mode; 65 else if (enable_off_mode) 66 pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n"); 67 68 return 0; 69 } 70 71 static int amx3_common_init(void) 72 { 73 gfx_pwrdm = pwrdm_lookup("gfx_pwrdm"); 74 per_pwrdm = pwrdm_lookup("per_pwrdm"); 75 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 76 77 if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm)) 78 return -ENODEV; 79 80 (void)clkdm_for_each(omap_pm_clkdms_setup, NULL); 81 82 /* CEFUSE domain can be turned off post bootup */ 83 cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm"); 84 if (!cefuse_pwrdm) 85 pr_err("PM: Failed to get cefuse_pwrdm\n"); 86 else if (omap_type() != OMAP2_DEVICE_TYPE_GP) 87 pr_info("PM: Leaving EFUSE power domain active\n"); 88 else 89 omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF); 90 91 return 0; 92 } 93 94 static int am33xx_suspend_init(void) 95 { 96 int ret; 97 98 gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm"); 99 100 if (!gfx_l4ls_clkdm) { 101 pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n"); 102 return -ENODEV; 103 } 104 105 ret = amx3_common_init(); 106 107 return ret; 108 } 109 110 static int am43xx_suspend_init(void) 111 { 112 int ret = 0; 113 114 ret = am43xx_map_scu(); 115 if (ret) { 116 pr_err("PM: Could not ioremap SCU\n"); 117 return ret; 118 } 119 120 ret = amx3_common_init(); 121 122 return ret; 123 } 124 125 static void amx3_pre_suspend_common(void) 126 { 127 omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF); 128 } 129 130 static void amx3_post_suspend_common(void) 131 { 132 int status; 133 /* 134 * Because gfx_pwrdm is the only one under MPU control, 135 * comment on transition status 136 */ 137 status = pwrdm_read_pwrst(gfx_pwrdm); 138 if (status != PWRDM_POWER_OFF) 139 pr_err("PM: GFX domain did not transition: %x\n", status); 140 } 141 142 static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long), 143 unsigned long args) 144 { 145 int ret = 0; 146 147 amx3_pre_suspend_common(); 148 ret = cpu_suspend(args, fn); 149 amx3_post_suspend_common(); 150 151 /* 152 * BUG: GFX_L4LS clock domain needs to be woken up to 153 * ensure thet L4LS clock domain does not get stuck in 154 * transition. If that happens L3 module does not get 155 * disabled, thereby leading to PER power domain 156 * transition failing 157 */ 158 159 clkdm_wakeup(gfx_l4ls_clkdm); 160 clkdm_sleep(gfx_l4ls_clkdm); 161 162 return ret; 163 } 164 165 static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), 166 unsigned long args) 167 { 168 int ret = 0; 169 170 /* Suspend secure side on HS devices */ 171 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 172 if (optee_available) 173 omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0); 174 else 175 omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND, 176 FLAG_START_CRITICAL, 177 0, 0, 0, 0, 0); 178 } 179 180 amx3_pre_suspend_common(); 181 scu_power_mode(scu_base, SCU_PM_POWEROFF); 182 ret = cpu_suspend(args, fn); 183 scu_power_mode(scu_base, SCU_PM_NORMAL); 184 185 if (!am43xx_check_off_mode_enable()) 186 amx3_post_suspend_common(); 187 188 /* 189 * Resume secure side on HS devices. 190 * 191 * Note that even on systems with OP-TEE available this resume call is 192 * issued to the ROM. This is because upon waking from suspend the ROM 193 * is restored as the secure monitor. On systems with OP-TEE ROM will 194 * restore OP-TEE during this call. 195 */ 196 if (omap_type() != OMAP2_DEVICE_TYPE_GP) 197 omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME, 198 FLAG_START_CRITICAL, 199 0, 0, 0, 0, 0); 200 201 return ret; 202 } 203 204 static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void) 205 { 206 if (soc_is_am33xx()) 207 return &am33xx_pm_sram; 208 else if (soc_is_am437x()) 209 return &am43xx_pm_sram; 210 else 211 return NULL; 212 } 213 214 void __iomem *am43xx_get_rtc_base_addr(void) 215 { 216 rtc_oh = omap_hwmod_lookup("rtc"); 217 218 return omap_hwmod_get_mpu_rt_va(rtc_oh); 219 } 220 221 static void am43xx_save_context(void) 222 { 223 } 224 225 static void am33xx_save_context(void) 226 { 227 omap_intc_save_context(); 228 } 229 230 static void am33xx_restore_context(void) 231 { 232 omap_intc_restore_context(); 233 } 234 235 static void am43xx_restore_context(void) 236 { 237 /* 238 * HACK: restore dpll_per_clkdcoldo register contents, to avoid 239 * breaking suspend-resume 240 */ 241 writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14)); 242 } 243 244 static void am43xx_prepare_rtc_suspend(void) 245 { 246 omap_hwmod_enable(rtc_oh); 247 } 248 249 static void am43xx_prepare_rtc_resume(void) 250 { 251 omap_hwmod_idle(rtc_oh); 252 } 253 254 static struct am33xx_pm_platform_data am33xx_ops = { 255 .init = am33xx_suspend_init, 256 .soc_suspend = am33xx_suspend, 257 .get_sram_addrs = amx3_get_sram_addrs, 258 .save_context = am33xx_save_context, 259 .restore_context = am33xx_restore_context, 260 .prepare_rtc_suspend = am43xx_prepare_rtc_suspend, 261 .prepare_rtc_resume = am43xx_prepare_rtc_resume, 262 .check_off_mode_enable = am33xx_check_off_mode_enable, 263 .get_rtc_base_addr = am43xx_get_rtc_base_addr, 264 }; 265 266 static struct am33xx_pm_platform_data am43xx_ops = { 267 .init = am43xx_suspend_init, 268 .soc_suspend = am43xx_suspend, 269 .get_sram_addrs = amx3_get_sram_addrs, 270 .save_context = am43xx_save_context, 271 .restore_context = am43xx_restore_context, 272 .prepare_rtc_suspend = am43xx_prepare_rtc_suspend, 273 .prepare_rtc_resume = am43xx_prepare_rtc_resume, 274 .check_off_mode_enable = am43xx_check_off_mode_enable, 275 .get_rtc_base_addr = am43xx_get_rtc_base_addr, 276 }; 277 278 static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) 279 { 280 if (soc_is_am33xx()) 281 return &am33xx_ops; 282 else if (soc_is_am437x()) 283 return &am43xx_ops; 284 else 285 return NULL; 286 } 287 288 int __init amx3_common_pm_init(void) 289 { 290 struct am33xx_pm_platform_data *pdata; 291 struct platform_device_info devinfo; 292 293 pdata = am33xx_pm_get_pdata(); 294 295 memset(&devinfo, 0, sizeof(devinfo)); 296 devinfo.name = "pm33xx"; 297 devinfo.data = pdata; 298 devinfo.size_data = sizeof(*pdata); 299 devinfo.id = -1; 300 platform_device_register_full(&devinfo); 301 302 return 0; 303 } 304