xref: /linux/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi (revision 44f57d78) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	soc {
17		usb0: usb@c9000000 {
18			status = "disabled";
19			compatible = "amlogic,meson-gxl-dwc3";
20			#address-cells = <2>;
21			#size-cells = <2>;
22			ranges;
23
24			clocks = <&clkc CLKID_USB>;
25			clock-names = "usb_general";
26			resets = <&reset RESET_USB_OTG>;
27			reset-names = "usb_otg";
28
29			dwc3: dwc3@c9000000 {
30				compatible = "snps,dwc3";
31				reg = <0x0 0xc9000000 0x0 0x100000>;
32				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
33				dr_mode = "host";
34				maximum-speed = "high-speed";
35				snps,dis_u2_susphy_quirk;
36				phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
37			};
38		};
39	};
40};
41
42&apb {
43	usb2_phy0: phy@78000 {
44		compatible = "amlogic,meson-gxl-usb2-phy";
45		#phy-cells = <0>;
46		reg = <0x0 0x78000 0x0 0x20>;
47		clocks = <&clkc CLKID_USB>;
48		clock-names = "phy";
49		resets = <&reset RESET_USB_OTG>;
50		reset-names = "phy";
51		status = "okay";
52	};
53
54	usb2_phy1: phy@78020 {
55		compatible = "amlogic,meson-gxl-usb2-phy";
56		#phy-cells = <0>;
57		reg = <0x0 0x78020 0x0 0x20>;
58		clocks = <&clkc CLKID_USB>;
59		clock-names = "phy";
60		resets = <&reset RESET_USB_OTG>;
61		reset-names = "phy";
62		status = "okay";
63	};
64
65	usb3_phy: phy@78080 {
66		compatible = "amlogic,meson-gxl-usb3-phy";
67		#phy-cells = <0>;
68		reg = <0x0 0x78080 0x0 0x20>;
69		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70		clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
71		clock-names = "phy", "peripheral";
72		resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
73		reset-names = "phy", "peripheral";
74		status = "okay";
75	};
76};
77
78&efuse {
79	clocks = <&clkc CLKID_EFUSE>;
80};
81
82&ethmac {
83	reg = <0x0 0xc9410000 0x0 0x10000
84	       0x0 0xc8834540 0x0 0x4>;
85
86	clocks = <&clkc CLKID_ETH>,
87		 <&clkc CLKID_FCLK_DIV2>,
88		 <&clkc CLKID_MPLL2>;
89	clock-names = "stmmaceth", "clkin0", "clkin1";
90
91	mdio0: mdio {
92		#address-cells = <1>;
93		#size-cells = <0>;
94		compatible = "snps,dwmac-mdio";
95	};
96};
97
98&aobus {
99	pinctrl_aobus: pinctrl@14 {
100		compatible = "amlogic,meson-gxl-aobus-pinctrl";
101		#address-cells = <2>;
102		#size-cells = <2>;
103		ranges;
104
105		gpio_ao: bank@14 {
106			reg = <0x0 0x00014 0x0 0x8>,
107			      <0x0 0x0002c 0x0 0x4>,
108			      <0x0 0x00024 0x0 0x8>;
109			reg-names = "mux", "pull", "gpio";
110			gpio-controller;
111			#gpio-cells = <2>;
112			gpio-ranges = <&pinctrl_aobus 0 0 14>;
113		};
114
115		uart_ao_a_pins: uart_ao_a {
116			mux {
117				groups = "uart_tx_ao_a", "uart_rx_ao_a";
118				function = "uart_ao";
119				bias-disable;
120			};
121		};
122
123		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
124			mux {
125				groups = "uart_cts_ao_a",
126				       "uart_rts_ao_a";
127				function = "uart_ao";
128				bias-disable;
129			};
130		};
131
132		uart_ao_b_pins: uart_ao_b {
133			mux {
134				groups = "uart_tx_ao_b", "uart_rx_ao_b";
135				function = "uart_ao_b";
136				bias-disable;
137			};
138		};
139
140		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
141			mux {
142				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
143				function = "uart_ao_b";
144				bias-disable;
145			};
146		};
147
148		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
149			mux {
150				groups = "uart_cts_ao_b",
151				       "uart_rts_ao_b";
152				function = "uart_ao_b";
153				bias-disable;
154			};
155		};
156
157		remote_input_ao_pins: remote_input_ao {
158			mux {
159				groups = "remote_input_ao";
160				function = "remote_input_ao";
161				bias-disable;
162			};
163		};
164
165		i2c_ao_pins: i2c_ao {
166			mux {
167				groups = "i2c_sck_ao",
168				       "i2c_sda_ao";
169				function = "i2c_ao";
170				bias-disable;
171			};
172		};
173
174		pwm_ao_a_3_pins: pwm_ao_a_3 {
175			mux {
176				groups = "pwm_ao_a_3";
177				function = "pwm_ao_a";
178				bias-disable;
179			};
180		};
181
182		pwm_ao_a_8_pins: pwm_ao_a_8 {
183			mux {
184				groups = "pwm_ao_a_8";
185				function = "pwm_ao_a";
186				bias-disable;
187			};
188		};
189
190		pwm_ao_b_pins: pwm_ao_b {
191			mux {
192				groups = "pwm_ao_b";
193				function = "pwm_ao_b";
194				bias-disable;
195			};
196		};
197
198		pwm_ao_b_6_pins: pwm_ao_b_6 {
199			mux {
200				groups = "pwm_ao_b_6";
201				function = "pwm_ao_b";
202				bias-disable;
203			};
204		};
205
206		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
207			mux {
208				groups = "i2s_out_ch23_ao";
209				function = "i2s_out_ao";
210				bias-disable;
211			};
212		};
213
214		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
215			mux {
216				groups = "i2s_out_ch45_ao";
217				function = "i2s_out_ao";
218				bias-disable;
219			};
220		};
221
222		spdif_out_ao_6_pins: spdif_out_ao_6 {
223			mux {
224				groups = "spdif_out_ao_6";
225				function = "spdif_out_ao";
226				bias-disable;
227			};
228		};
229
230		spdif_out_ao_9_pins: spdif_out_ao_9 {
231			mux {
232				groups = "spdif_out_ao_9";
233				function = "spdif_out_ao";
234				bias-disable;
235			};
236		};
237
238		ao_cec_pins: ao_cec {
239			mux {
240				groups = "ao_cec";
241				function = "cec_ao";
242				bias-disable;
243			};
244		};
245
246		ee_cec_pins: ee_cec {
247			mux {
248				groups = "ee_cec";
249				function = "cec_ao";
250				bias-disable;
251			};
252		};
253	};
254};
255
256&cec_AO {
257	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
258	clock-names = "core";
259};
260
261&clkc_AO {
262	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
263	clocks = <&xtal>, <&clkc CLKID_CLK81>;
264	clock-names = "xtal", "mpeg-clk";
265};
266
267&gpio_intc {
268	compatible = "amlogic,meson-gpio-intc",
269		     "amlogic,meson-gxl-gpio-intc";
270	status = "okay";
271};
272
273&hdmi_tx {
274	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
275	resets = <&reset RESET_HDMITX_CAPB3>,
276		 <&reset RESET_HDMI_SYSTEM_RESET>,
277		 <&reset RESET_HDMI_TX>;
278	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
279	clocks = <&clkc CLKID_HDMI_PCLK>,
280		 <&clkc CLKID_CLK81>,
281		 <&clkc CLKID_GCLK_VENCI_INT0>;
282	clock-names = "isfr", "iahb", "venci";
283};
284
285&sysctrl {
286	clkc: clock-controller {
287		compatible = "amlogic,gxl-clkc";
288		#clock-cells = <1>;
289		clocks = <&xtal>;
290		clock-names = "xtal";
291	};
292};
293
294&i2c_A {
295	clocks = <&clkc CLKID_I2C>;
296};
297
298&i2c_AO {
299	clocks = <&clkc CLKID_AO_I2C>;
300};
301
302&i2c_B {
303	clocks = <&clkc CLKID_I2C>;
304};
305
306&i2c_C {
307	clocks = <&clkc CLKID_I2C>;
308};
309
310&periphs {
311	pinctrl_periphs: pinctrl@4b0 {
312		compatible = "amlogic,meson-gxl-periphs-pinctrl";
313		#address-cells = <2>;
314		#size-cells = <2>;
315		ranges;
316
317		gpio: bank@4b0 {
318			reg = <0x0 0x004b0 0x0 0x28>,
319			      <0x0 0x004e8 0x0 0x14>,
320			      <0x0 0x00520 0x0 0x14>,
321			      <0x0 0x00430 0x0 0x40>;
322			reg-names = "mux", "pull", "pull-enable", "gpio";
323			gpio-controller;
324			#gpio-cells = <2>;
325			gpio-ranges = <&pinctrl_periphs 0 0 100>;
326		};
327
328		emmc_pins: emmc {
329			mux {
330				groups = "emmc_nand_d07",
331				       "emmc_cmd",
332				       "emmc_clk";
333				function = "emmc";
334				bias-disable;
335			};
336		};
337
338		emmc_ds_pins: emmc-ds {
339			mux {
340				groups = "emmc_ds";
341				function = "emmc";
342				bias-disable;
343			};
344		};
345
346		emmc_clk_gate_pins: emmc_clk_gate {
347			mux {
348				groups = "BOOT_8";
349				function = "gpio_periphs";
350				bias-pull-down;
351			};
352		};
353
354		nor_pins: nor {
355			mux {
356				groups = "nor_d",
357				       "nor_q",
358				       "nor_c",
359				       "nor_cs";
360				function = "nor";
361				bias-disable;
362			};
363		};
364
365		spi_pins: spi-pins {
366			mux {
367				groups = "spi_miso",
368					"spi_mosi",
369					"spi_sclk";
370				function = "spi";
371				bias-disable;
372			};
373		};
374
375		spi_ss0_pins: spi-ss0 {
376			mux {
377				groups = "spi_ss0";
378				function = "spi";
379				bias-disable;
380			};
381		};
382
383		sdcard_pins: sdcard {
384			mux {
385				groups = "sdcard_d0",
386				       "sdcard_d1",
387				       "sdcard_d2",
388				       "sdcard_d3",
389				       "sdcard_cmd",
390				       "sdcard_clk";
391				function = "sdcard";
392				bias-disable;
393			};
394		};
395
396		sdcard_clk_gate_pins: sdcard_clk_gate {
397			mux {
398				groups = "CARD_2";
399				function = "gpio_periphs";
400				bias-pull-down;
401			};
402		};
403
404		sdio_pins: sdio {
405			mux {
406				groups = "sdio_d0",
407				       "sdio_d1",
408				       "sdio_d2",
409				       "sdio_d3",
410				       "sdio_cmd",
411				       "sdio_clk";
412				function = "sdio";
413				bias-disable;
414			};
415		};
416
417		sdio_clk_gate_pins: sdio_clk_gate {
418			mux {
419				groups = "GPIOX_4";
420				function = "gpio_periphs";
421				bias-pull-down;
422			};
423		};
424
425		sdio_irq_pins: sdio_irq {
426			mux {
427				groups = "sdio_irq";
428				function = "sdio";
429				bias-disable;
430			};
431		};
432
433		uart_a_pins: uart_a {
434			mux {
435				groups = "uart_tx_a",
436				       "uart_rx_a";
437				function = "uart_a";
438				bias-disable;
439			};
440		};
441
442		uart_a_cts_rts_pins: uart_a_cts_rts {
443			mux {
444				groups = "uart_cts_a",
445				       "uart_rts_a";
446				function = "uart_a";
447				bias-disable;
448			};
449		};
450
451		uart_b_pins: uart_b {
452			mux {
453				groups = "uart_tx_b",
454				       "uart_rx_b";
455				function = "uart_b";
456				bias-disable;
457			};
458		};
459
460		uart_b_cts_rts_pins: uart_b_cts_rts {
461			mux {
462				groups = "uart_cts_b",
463				       "uart_rts_b";
464				function = "uart_b";
465				bias-disable;
466			};
467		};
468
469		uart_c_pins: uart_c {
470			mux {
471				groups = "uart_tx_c",
472				       "uart_rx_c";
473				function = "uart_c";
474				bias-disable;
475			};
476		};
477
478		uart_c_cts_rts_pins: uart_c_cts_rts {
479			mux {
480				groups = "uart_cts_c",
481				       "uart_rts_c";
482				function = "uart_c";
483				bias-disable;
484			};
485		};
486
487		i2c_a_pins: i2c_a {
488			mux {
489				groups = "i2c_sck_a",
490				     "i2c_sda_a";
491				function = "i2c_a";
492				bias-disable;
493			};
494		};
495
496		i2c_b_pins: i2c_b {
497			mux {
498				groups = "i2c_sck_b",
499				      "i2c_sda_b";
500				function = "i2c_b";
501				bias-disable;
502			};
503		};
504
505		i2c_c_pins: i2c_c {
506			mux {
507				groups = "i2c_sck_c",
508				      "i2c_sda_c";
509				function = "i2c_c";
510				bias-disable;
511			};
512		};
513
514		eth_pins: eth_c {
515			mux {
516				groups = "eth_mdio",
517				       "eth_mdc",
518				       "eth_clk_rx_clk",
519				       "eth_rx_dv",
520				       "eth_rxd0",
521				       "eth_rxd1",
522				       "eth_rxd2",
523				       "eth_rxd3",
524				       "eth_rgmii_tx_clk",
525				       "eth_tx_en",
526				       "eth_txd0",
527				       "eth_txd1",
528				       "eth_txd2",
529				       "eth_txd3";
530				function = "eth";
531				bias-disable;
532			};
533		};
534
535		eth_link_led_pins: eth_link_led {
536			mux {
537				groups = "eth_link_led";
538				function = "eth_led";
539				bias-disable;
540			};
541		};
542
543		eth_act_led_pins: eth_act_led {
544			mux {
545				groups = "eth_act_led";
546				function = "eth_led";
547			};
548		};
549
550		pwm_a_pins: pwm_a {
551			mux {
552				groups = "pwm_a";
553				function = "pwm_a";
554				bias-disable;
555			};
556		};
557
558		pwm_b_pins: pwm_b {
559			mux {
560				groups = "pwm_b";
561				function = "pwm_b";
562				bias-disable;
563			};
564		};
565
566		pwm_c_pins: pwm_c {
567			mux {
568				groups = "pwm_c";
569				function = "pwm_c";
570				bias-disable;
571			};
572		};
573
574		pwm_d_pins: pwm_d {
575			mux {
576				groups = "pwm_d";
577				function = "pwm_d";
578				bias-disable;
579			};
580		};
581
582		pwm_e_pins: pwm_e {
583			mux {
584				groups = "pwm_e";
585				function = "pwm_e";
586				bias-disable;
587			};
588		};
589
590		pwm_f_clk_pins: pwm_f_clk {
591			mux {
592				groups = "pwm_f_clk";
593				function = "pwm_f";
594				bias-disable;
595			};
596		};
597
598		pwm_f_x_pins: pwm_f_x {
599			mux {
600				groups = "pwm_f_x";
601				function = "pwm_f";
602				bias-disable;
603			};
604		};
605
606		hdmi_hpd_pins: hdmi_hpd {
607			mux {
608				groups = "hdmi_hpd";
609				function = "hdmi_hpd";
610				bias-disable;
611			};
612		};
613
614		hdmi_i2c_pins: hdmi_i2c {
615			mux {
616				groups = "hdmi_sda", "hdmi_scl";
617				function = "hdmi_i2c";
618				bias-disable;
619			};
620		};
621
622		i2s_am_clk_pins: i2s_am_clk {
623			mux {
624				groups = "i2s_am_clk";
625				function = "i2s_out";
626				bias-disable;
627			};
628		};
629
630		i2s_out_ao_clk_pins: i2s_out_ao_clk {
631			mux {
632				groups = "i2s_out_ao_clk";
633				function = "i2s_out";
634				bias-disable;
635			};
636		};
637
638		i2s_out_lr_clk_pins: i2s_out_lr_clk {
639			mux {
640				groups = "i2s_out_lr_clk";
641				function = "i2s_out";
642				bias-disable;
643			};
644		};
645
646		i2s_out_ch01_pins: i2s_out_ch01 {
647			mux {
648				groups = "i2s_out_ch01";
649				function = "i2s_out";
650				bias-disable;
651			};
652		};
653		i2sout_ch23_z_pins: i2sout_ch23_z {
654			mux {
655				groups = "i2sout_ch23_z";
656				function = "i2s_out";
657				bias-disable;
658			};
659		};
660
661		i2sout_ch45_z_pins: i2sout_ch45_z {
662			mux {
663				groups = "i2sout_ch45_z";
664				function = "i2s_out";
665				bias-disable;
666			};
667		};
668
669		i2sout_ch67_z_pins: i2sout_ch67_z {
670			mux {
671				groups = "i2sout_ch67_z";
672				function = "i2s_out";
673				bias-disable;
674			};
675		};
676
677		spdif_out_h_pins: spdif_out_ao_h {
678			mux {
679				groups = "spdif_out_h";
680				function = "spdif_out";
681				bias-disable;
682			};
683		};
684	};
685
686	eth-phy-mux {
687		compatible = "mdio-mux-mmioreg", "mdio-mux";
688		#address-cells = <1>;
689		#size-cells = <0>;
690		reg = <0x0 0x55c 0x0 0x4>;
691		mux-mask = <0xffffffff>;
692		mdio-parent-bus = <&mdio0>;
693
694		internal_mdio: mdio@e40908ff {
695			reg = <0xe40908ff>;
696			#address-cells = <1>;
697			#size-cells = <0>;
698
699			internal_phy: ethernet-phy@8 {
700				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
701				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
702				reg = <8>;
703				max-speed = <100>;
704			};
705		};
706
707		external_mdio: mdio@2009087f {
708			reg = <0x2009087f>;
709			#address-cells = <1>;
710			#size-cells = <0>;
711		};
712	};
713};
714
715&pwrc_vpu {
716	resets = <&reset RESET_VIU>,
717		 <&reset RESET_VENC>,
718		 <&reset RESET_VCBUS>,
719		 <&reset RESET_BT656>,
720		 <&reset RESET_DVIN_RESET>,
721		 <&reset RESET_RDMA>,
722		 <&reset RESET_VENCI>,
723		 <&reset RESET_VENCP>,
724		 <&reset RESET_VDAC>,
725		 <&reset RESET_VDI6>,
726		 <&reset RESET_VENCL>,
727		 <&reset RESET_VID_LOCK>;
728	clocks = <&clkc CLKID_VPU>,
729	         <&clkc CLKID_VAPB>;
730	clock-names = "vpu", "vapb";
731	/*
732	 * VPU clocking is provided by two identical clock paths
733	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
734	 * free mux to safely change frequency while running.
735	 * Same for VAPB but with a final gate after the glitch free mux.
736	 */
737	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
738			  <&clkc CLKID_VPU_0>,
739			  <&clkc CLKID_VPU>, /* Glitch free mux */
740			  <&clkc CLKID_VAPB_0_SEL>,
741			  <&clkc CLKID_VAPB_0>,
742			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
743	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
744				 <0>, /* Do Nothing */
745				 <&clkc CLKID_VPU_0>,
746				 <&clkc CLKID_FCLK_DIV4>,
747				 <0>, /* Do Nothing */
748				 <&clkc CLKID_VAPB_0>;
749	assigned-clock-rates = <0>, /* Do Nothing */
750			       <666666666>,
751			       <0>, /* Do Nothing */
752			       <0>, /* Do Nothing */
753			       <250000000>,
754			       <0>; /* Do Nothing */
755};
756
757&saradc {
758	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
759	clocks = <&xtal>,
760		 <&clkc CLKID_SAR_ADC>,
761		 <&clkc CLKID_SAR_ADC_CLK>,
762		 <&clkc CLKID_SAR_ADC_SEL>;
763	clock-names = "clkin", "core", "adc_clk", "adc_sel";
764};
765
766&sd_emmc_a {
767	clocks = <&clkc CLKID_SD_EMMC_A>,
768		 <&clkc CLKID_SD_EMMC_A_CLK0>,
769		 <&clkc CLKID_FCLK_DIV2>;
770	clock-names = "core", "clkin0", "clkin1";
771	resets = <&reset RESET_SD_EMMC_A>;
772};
773
774&sd_emmc_b {
775	clocks = <&clkc CLKID_SD_EMMC_B>,
776		 <&clkc CLKID_SD_EMMC_B_CLK0>,
777		 <&clkc CLKID_FCLK_DIV2>;
778	clock-names = "core", "clkin0", "clkin1";
779	resets = <&reset RESET_SD_EMMC_B>;
780};
781
782&sd_emmc_c {
783	clocks = <&clkc CLKID_SD_EMMC_C>,
784		 <&clkc CLKID_SD_EMMC_C_CLK0>,
785		 <&clkc CLKID_FCLK_DIV2>;
786	clock-names = "core", "clkin0", "clkin1";
787	resets = <&reset RESET_SD_EMMC_C>;
788};
789
790&simplefb_hdmi {
791	clocks = <&clkc CLKID_HDMI_PCLK>,
792		 <&clkc CLKID_CLK81>,
793		 <&clkc CLKID_GCLK_VENCI_INT0>;
794};
795
796&spicc {
797	clocks = <&clkc CLKID_SPICC>;
798	clock-names = "core";
799	resets = <&reset RESET_PERIPHS_SPICC>;
800	num-cs = <1>;
801};
802
803&spifc {
804	clocks = <&clkc CLKID_SPI>;
805};
806
807&uart_A {
808	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
809	clock-names = "xtal", "pclk", "baud";
810};
811
812&uart_AO {
813	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
814	clock-names = "xtal", "pclk", "baud";
815};
816
817&uart_AO_B {
818	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
819	clock-names = "xtal", "pclk", "baud";
820};
821
822&uart_B {
823	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
824	clock-names = "xtal", "pclk", "baud";
825};
826
827&uart_C {
828	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
829	clock-names = "xtal", "pclk", "baud";
830};
831
832&vpu {
833	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
834	power-domains = <&pwrc_vpu>;
835};
836